Cambridge-1 GPU close-up

AI could be key to optimising chip design, Nvidia says

Image credit: Nvidia

Nvidia Corp has released a paper showing how a combination of artificial intelligence (AI) techniques could find the best ways to place transistors on silicon chips.

Nvidia Corp, the world's leading designer of computer chips used in AI, has shown new research that explains how artificial intelligence tools can be used to improve chip design.

In the paper, called 'AutoDMP: Automated DREAMPlace-based Macro Placement', the Nvidia research team proposed an AI-based methodology to optimise the placement of transistors on silicon chips, thereby improving their cost, speed and power consumption. 

Billions of tiny switches called transistors are placed on a piece of silicon to create what we know as silicon chips, and so the placement of these switches has a great impact on the capabilities of the chips. 

At the moment, chip design engineers use complex design software from firms like Synopsys Inc and Cadence Design Systems Inc to optimise the placement of those transistors. However, according to Nvidia, AI tools could provide an additional source of insight during these design processes. 


Conceptual view of the two-level exploration of the mixed-size placement landscape/Nvidia

Image credit: Nvidia

The Nvidia research used a technique known as reinforcement learning and combined it with a second layer of artificial intelligence on top to improve the process of placing transistors on chips. 

The research was based on a previous effort developed by University of Texas researchers. It also aimed to improve on a 2021 paper by Alphabet Inc's Google, which covered a similar topic. 

The new methodology, named Automated DREAMPlace-based Macro Placement (AutoDMP), uses ML-based multi-objective optimisation and analytical mixed-size placers accelerated by graphics processing units (GPUs) to search through a vast design space and select the best placement for transistors. 

Using AutoDMP, the designers were able to generate placement solutions in only a few hours, achieving "results comparable to commercial tools and superior to open-source academic tools", according to the team.

AutoDMP is also computationally efficient, the paper said, as it can optimise a design with 2.7 million cells and 320 macros in three hours on a single NVIDIA DGX Station A100. 

These findings could be key to improving chip manufacturing processes, as these are currently becoming more expensive to produce due to the complexity of their design.

"You're no longer actually getting an economy from that scaling," Nvidia chief scientist Bill Dally said. "To continue to move forward and to deliver more value to customers, we can't get it from cheaper transistors. We have to get it by being more clever on the design." 

Nvidia was among the semiconductor manufacturers ordered to halt exports of AI silicon chips to China, as part of the technology and trade dispute between Washington and Beijing. The restrictions cover Nvidia’s A100 and forthcoming H100 integrated circuits, and any systems that include them.

In August, the US also prohibited the export of four technologies tied to semiconductor manufacturing, citing they were “vital to national security” and signed a “historic” bill aimed at boosting the domestic production of semiconductors. 

Sign up to the E&T News e-mail to get great stories like this delivered to your inbox every day.

Recent articles