Silicon chip fabrication

Welcome to the Angstrom Age

Image credit: Rainer Plendl/Dreamstime

Well, not quite. There’s a growing gap between names and reality in silicon design.

I used to joke that we’d run out nanometres before we run out of Moore’s Law. Well, it’s happened. Now we’re in the Angstrom Age, apparently. Yet the dimensions that determine logic density remain at least an order of magnitude larger than 1nm and are likely to stay this way for a while, possibly for good.

At the International Solid State Circuits Conference (ISSCC) last week, AMD CEO Lisa Su pointed to how increasing cost and slowing progress in physical scaling is changing not how they design their processors but the architecture of the high-performance computers some of them go into. To some extent the metric has gone back to performance rather than scaling, in much the same fashion as the end of the 1990s when Intel used Moore’s Law as a proxy for speed and not just logic density.

”Moore's Law has slowed down, it is becoming much, much harder to get density, performance, as well as efficiency,” Su said. “We've been increasing the performance on the order of doubling every two to two-and-a-half years or so. So with all of the conversation about Moore's Law slowing, there's been a tremendous amount of innovation on architecture, on packaging, on increasing die sizes and on power such that we're able to do that.”

Because power has been increasing, there is now a far greater focus on dedicated accelerators, as these are more energy-efficient than general-purpose processors – just as long as you have software that can take advantage of the customised circuitry. “There has been a lot of work and will continue to be a lot of work with domain-specific computation,” Su noted.

Packaging comes into play because of the way that data movement saps both performance and electricity. If you can stack memories and processors on top of each other, you cut the distance the large quantities of data need to travel to get to and from the processor elements. All of this helps compensate for the fact that transistors are not getting much smaller year on year and, as a result, not increasing density at the classic rate of a doubling every two years. 

The process node introduced five years ago had a minimum metal pitch, the distance between lines used to carry current between devices, of 40nm. At the current generation it is around 22nm. In practice the spacing between transistors is somewhat larger, not least because you generally need more than one fin in a finFET. But because the metal lines run well over the top of the active layer, reducing this pitch does result in an overall benefit to density and that is not entirely out of line with Moore’s Law, which has helped with the nips and tucks. 

However, the transistors have not shrunk as fast as advertised for a while. Gate length dropped dramatically in the 2000s and then slowed. A decade ago, the IEEE’s International Roadmap for Devices and Systems (IRDS) group determined that transistors would have a gate no longer than 4nm to stay on Moore’s Law. In practice, it is more like 18nm. Things get worse in the coming years as metal pitch will likely only get down to 12nm even a decade from now.

Progress has come and will continue to be delivered with a succession of clever nips and tucks, such as cutting out the need for dummy elements to break up independent logic cells and additions to the routing layers that wire the transistors together, as demonstrated by Imec at the International Electron Device Meeting (IEDM) in December. 

To signal progress, Imec’s latest roadmap substitutes A for angstrom in place of the N for nanometre the research institute has been using to name process nodes for the past decade. The issue Imec faced is that currently the bleeding edge is N3, which equates to the 3nm process being deployed by Samsung and TSMC. Intel used to be on a different, and slightly more realistic numbering system. But as the company fell behind with getting processes up and running, it has aligned with the other leading fab owners. 

N2 is meant to start prototype production next year and will be followed by the first of the ‘angstrom’ technologies two years later. These new processes take advantage of the gate-all-around structure, which more or less rotates the finFET through 90° and, in principle, makes it easier to make the transistors a bit narrower. After about four generations, further improvements there run out of steam. At that point, the A5 generation that should hit the streets in a decade’s time will start to stack transistors on top of each other 

Bizarrely, we get close to running out of angstroms, or at least the A designation, sometime around 2038. So at that point, despite hardly still having hardly any of the key dimensions being smaller than 10nm, we will presumably be in the Pico Period. However, as that’s a thousand times smaller than nano, it might have a bit more runway than the angstrom.

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