Wafer of new 5nm transistors

IBM researchers fit 30 billion transistors on fingernail-sized chip

Image credit: IBM

Researchers belonging to the IBM-led Research Alliance have developed a new method to build silicon nanosheet transistors. This allows 5nm chips, which could accelerate the development of data-intensive applications such as virtual reality.

Two years ago, the researchers developed a 7nm test node chip, which contained 20 billion transistors. Their latest research, which will be presented at the 2017 Symposia on VLSI Technology and Circuits in Kyoto, Japan, pushes their remarkable achievement further, with the development of 5nm transistors.

5nm transistors were assumed to mark the end of Moore’s Law; the number of components in a dense integrated circuit doubling approximately every two years. Due to the time and expense of developing such small transistors, the 5nm node was expected to take longer than two years to reach the market.

Closeup of new 5nm transistors


Image credit: IBM

IBM Research has been exploring nanosheet semiconductor technology for more than a decade and this is the first time that the superior electrical properties of stacked nanosheet devices have been demonstrated, compared with traditionally structured devices.

“For business and society to meet the demands of cognitive and cloud computing in the coming years, advancement in semiconductor technology is essential,” said Dr Arvind Krishna, director of IBM Research.

IBM engineers worked with Samsung and other partners at the Research Alliance (based at the State University of New York (SUNY) NanoTech Complex) on the project. They began by using stacks of silicon nanosheets as the basic structure for the transistor, rather than the standard FinFET structure, used in modern processors for up to 7nm node chips.

Using the same approach as for 7nm technology, Extreme Ultraviolet lithography, the researchers were able to adjust the width of the nanosheets in order to fine-tune performance and power for specialised circuits. This demonstrated the versatility of the IBM nanosheet transistors, compared with conventional FinFET chips, which cannot provide increased power for additional performance.

5nm technology can deliver 40 per cent performance enhancement at fixed power, compared with widely available 10nm technology, or 75 per cent power savings.

This improvement allows a huge increase in performance, which could enable and accelerate computationally intense applications, such as deep learning, virtual reality and the Internet of Things (IoT). This would also result in significant power savings smartphones and other devices, which could last two to three times longer before charging.

“We believe that enabling the first 5nm transistor is a significant milestone for the entire semiconductor industry as we continue to push beyond the limitations of our current capabilities,” said Dr Bahgat Sammakia, interim president of SUNY Polytechnic Institute.

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