A significant step towards single microwatt power consumption by analogue interfaces has been made by a team of Spanish researchers.
The ultimate aim is to develop smart wireless sensors for biological or environmental conditions that can operate by harvesting ambient energy such as body heat or movement.
Last year, researchers from the Public University of Navarre (UPNA) in Spain won best paper at the International Conference on Sensing Technology (ICST) for their design for an analogue-to-digital converter (ADC) that reduced power consumption to just over 2µW.
At 100ksample/s and a resolution of 8bit, the design produced by telecoms student Iñigo Cenoz-Villanueva and his supervisor Professor Antonio López-Martín, achieved a power efficiency close to an order of magnitude better than many discrete commercial chips.
In common with a number of other research teams looking at low-energy ADCs, Cenoz-Villanueva and López-Martín focused on the successive approximation architecture, in which the circuitry attempts to match the analogue input by trial and error over a number of clock cycles.
These typically consume less power than other techniques at the low sample-rates needed for biomedical and environmental sensing. However, these designs rely on a bank of capacitors that are selectively charged to produce the right matching voltage, which consumes the bulk of the energy.
“We changed the way the capacitors are switched in this kind of ADC, so that the voltage variations of the capacitors that are switched is much lower. This decreases the energy required to switch them,” said López-Martín.
The design is based on an ‘old’ process technology – 0.5µm – operating at a voltage of 1.5V, López-Martín added. “The circuit could be translated to deep-submicron processes for even lower power as the supply voltage can be decreased.”
Using a 0.18µm process operating at 1V, researchers from Xidian University in Xi’an, China believe they will be able to develop an ADC that consumes a little over 3µW but with a higher resolution of 10bit and double the sample rate of the UPNA design.
At the International Solid State Circuits Conference in San Francisco, researchers from MIT reversed the order in which the successive-approximation process operates to bring average power consumption into the nanowatt region for a 16ksample/s ADC.
The converter uses the previous sample to estimate the value of the next and then uses successively larger changes in capacitance to produce the new result. The result is that larger capacitors don’t need to be discharged between each sample.