National Instruments' LabVIEW 2012 introduces several new features

National Instruments unveils new version of flagship software

Mobile apps for display and control on an iPad, system design templates and online training are among the new features included in the latest version of National Instruments’ LabVIEW software.

LabVIEW 2012 was launched at this year’s NI Week, the company’s annual conference held in Austin, Texas. This latest version of the company’s graphical system design software provides recommended application architectures designed to save time, ensure scalability and lower maintenance costs. Also included are stability improvements and environment enhancements derived directly from customer feedback designed to increase productivity and support for a number of new pieces of hardware such as the new RF vector signal transceiver.

“Building a system fast is important, but it’s equally important to build it right – that means using solid architectures and proven development practices,” said Dr James Truchard, President, CEO and Co-founder of National Instruments. “New features and resources in LabVIEW 2012 promote training and drive development practices to help our customers deliver high-performance and high-quality systems in less time, thereby minimising development and maintenance costs.”

The company also announced the release of the LabVIEW FPGA IP Builder add-on, which uses Xilinx Vivado High-Level Synthesis technology to simplify high-performance FPGA algorithm design. This new add-on reduces the need for manual optimisation of high-performance algorithms. Instead the software automatically generates a hardware implementation to meet user requirements.

“Our vision for the LabVIEW platform is to empower domain experts to represent their algorithms using natural programming paradigms and provide a seamless path for deploying to high-performance hardware,” said David Fuller, Vice President of Applications and Embedded Software for NI. “High-level synthesis technology is central to this vision – it empowers system designers to spend less time optimising their FPGA algorithms and more time innovating.

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