Chipmakers want to cut costs by moving to pizza-sized wafers, but could it prove to be an expensive mistake?
In 1975, Intel co-founder Gordon Moore stood in front of an audience of electronics engineers from around the world to make a small but significant correction to his famous mid-1960s observation about the rapidly increasing density of silicon chips: the pace would slow from doubling every year to doubling every two years. Some 35 years later, it is still true enough for people to refer to it as 'Moore's Law' however, during the same speech, he found time to make other predictions, which have not fared so well.
Moore used 15 years of historical data the young industry had already amassed to predict how big the wafers on which chips are made would become – they had grown from tiny slivers to be 75mm-diameter discs by 1975. Had this trend continued, by year 2000 fabs would have been working with dinner table-sized wafers. Instead, by that time fabs were only just switching to use wafers that were the diameter of a conventional vinyl LP record. When Moore gave his talk at the International Electron Devices Meeting (IEDM), the chips themselves were still growing quite rapidly. Wafers were getting bigger to accommodate devices that had grown from a couple of millimetres to being well on the order of a centimetre or more across. Then the pace slowed dramatically. Since the start of the 1990s, the maximum size of a silicon chip has barely increased at all because of the way that manufacturing yield still depends heavily on how large the die is.
Only a few, such as Intel's Itanium processors for large servers, reach that maximum. The sweet spot in terms of die size versus random defect density – and therefore yield – has remained stuck in the 100-150mm2 region for more than 20 years.
As a result, the pressure on wafer size eased up and the pace slowed dramatically – just two expansions in the past 20 years – but it has not stopped completely. This is for one good reason. Bob Johnson, vice president of research at Gartner, explained at the recent Semicon West show in San Francisco: 'It boils down to one thing, and it doesn't have a damn thing to do with Moore's Law. It's purely about cost. Yes, there is a lot of sophisticated technology needed to make these transitions happen, but the driving factor is cost.'
The effect on cost overall is not huge, but it helps. Johnson points out that between 1980 and 2010, there were 14 changes in process geometry. Decreasing by roughly square root-two every time, minimum feature sizes scaled down from around 3µm to almost 30nm during that period and areal density doubled. 'Each node change generated close to a 30 per cent cost saving,' he says.
With every node change there is still a hidden increase in cost. Every time there is a node change, chipmakers have to buy increasingly sophisticated processing equipment and put the wafers through a more complex sequence of steps to create the ever smaller transistors. During the 1980s and 1990s the increase in wafer-processing cost for a given wafer size was approximately 12 per cent per generation, or 5.5 per cent per year; but they could claw back some savings with an increase in the wafer size.
'Generally, each wafer transition was worth just one year of cost scaling,' Gartner's Bob Johnson claims. It is not a huge saving, but still worth having. For example, the increase from 200mm to 300mm wafers carried out at the beginning of the past decade more or less doubled the number of chips per wafer but the operating costs rose by nowhere near that amount. As a result, once the technology became mature, a foundry with a 300mm line could outcompete one that has access only to 200mm equipment. A sense of urgency has now developed among some of the largest chipmakers to take the next step from 300mm to 450mm. At the International Electronics Forum last year, the chief technology officer of foundry TSMC Jack Sun gave the view that the move to 450mm was vital to keeping wafer prices under control in the face of other rising costs.
The jumps in wafer cost from node to node have accelerated to 20 per cent per generation on average in the past decade; and the increase is far greater for the upcoming 20nm process than for any previous generation. The rise is so large that it threatens the economics of the business if the projections become reality. International Business Strategies has estimated an increase of close to 70 per cent for the 20nm process over its 28nm predecessor that is now ramping up at TSMC, and expected to go into production soon at GlobalFoundries. The 14nm process is likely to suffer a similar increase: 60 per cent. There is even worse news: 450mm will happen too late to help these nodes and may not happen, ever.
The 2008 recession delayed the move to 450mm, originally slated to start in 2012. In principle, the delay is only a couple of years. Hans Lebon, vice president of process R&D at Belgian research institute IMEC, says: 'We could have pilot lines in the 2013-14 timeframe. And production facilities in 2016-17 timeframe.' Says Rick Wallace, president and CEO of wafer-inspection company KLA-Tencor, 'If I had to bet I would say it's [going to be] 2015 before we see 450mm.'
As a result, the shift to 450mm might not be underway until the 10nm process is ready to roll. A combination of timescale, technological problems and history conspires to throw even that plan off course. 'Right now we are at the feasibility stage,' adds Bob Johnson at Gartner. 'We don't know if we can do it or not. And once we put in pilot lines the development costs start going through the roof.'
A model put together by analyst firm IC Knowledge projects cost-savings similar to those achieved with the move from 200mm to 300mm. But the people responsible for making the equipment that could realise this saving are not so sure.
Brian Trafas, chief marketing officer of KLA-Tencor, says: 'There is a big difference in the way that area and beam-scanning tools work.' Many of the steps in chipmaking are area-based: blowing a volatile gas mixture across the surface of a wafer to dope the semiconducting layers underneath or sputtering metal to form tiny wires; but these are now by far the cheapest tools and processes in the fab. Most of the cost now goes into lithography, which is on the way to costing $100m for each fab, because it relies on repeated laser scanning across a small portion of the wafer. This part of the process does not readily benefit from an increase in wafer area. Inspection tools have a similar problem. 'A lot of our tools are scanning tools. The question is: how do we scale? And how do we drive the productivity improvement?' asks Brian Trafas at KLA-Tencor.
Some of the claims being made to justify a shift to 450mm avoid any discussion of equipment prices, and focus on more marginal savings. At the Semicon Asia event, Shang-Yi Chiang, TSMC's head of R&D, used a 25 per cent reduction in labour to justify the company's continuing push for 450mm production. The schedule slippage for 450mm so far, however, makes the return on investment look increasingly shaky for anyone involved. The silicon industry is now running out of room at the bottom. It is a long way from physicist Richard Feynman's 1959 claim that there is plenty of room down there. 'Going forward, how many nodes do we have?' Gartner's Bob Johnson asks. 'How many nodes can we go past the 10nm level? There are definite technology brick walls.'
Professor Mike Kelly of the Centre for Advanced Photonics at the University of Cambridge has put some numbers on where the limits lie in a paper for Nanotechnology journal published earlier this year. For the manufacturing techniques used in electronics and photonics, 'intrinsic unmanufacturability', as Kelly terms it, happens as we approach 7nm design rules – just one node past 10nm. An optimistic scenario puts 450mm's lifetime at just four nodes.
'We could reasonably look at 10 nodes of life for 300mm tools – I would submit that 450mm will end up being a single-node product,' Gartner's Bob Johnson argues, adding that the projections for the payback on 300mm were not quite what anyone expected. 'At 300mm, we didn't realise market growth was starting to slow. In the 1990s, the average annual growth was 17 per cent – now it is 6 per cent.'
The payback problem is nowhere near as problematic for the chipmakers as it is for the companies that supply them equipment. They recall only too well who ended up paying the price of the 300mm transition. Steve Newberry, president and CEO of Lam Research, another equipment supplier, says: 'At 300mm you had companies making threats to the equipment suppliers to make it happen – and we had several false starts.'
Every time the chipmakers decided they were not ready for 300mm, the equipment manufacturers had to swallow the development cost of the tools they had put together but still be ready to support the transition when it happened or be left out in the cold for good. Even then, they encountered a much reduced customer base.
The 300mm transition winnowed out a large number of integrated device manufacturers – companies that both design and make their own chips – because, although they are cheaper to operate on a per-chip basis, they need massive amounts of capital to build.
Paolo Gargini, director of Intel's technology strategy, argues that the shift to 450mm will not make a huge difference to the balance of power. 'The analysts say eight or ten companies can afford it,' he said in an attempt to reassure equipment makers at Semicon West. 'You shouldn't worry about it. The top ten companies already own 85 per cent of the industry. It just means 85 per cent of the industry involved in manufacturing could go to 450mm.'
Johnson agrees that the shift to 450mm may not mean a further IDM cull: 'The purpose of 450mm is to reduce cost: 450mm will cost less per unit output, or it will fail. 450mm could reduce the number of companies who can build fabs: but that has already happened with 300mm. All 450mm really does is make it easier to stay in the game: it's cheaper for the same output.'
The question is whether, if they decide to push ahead, the chipmakers can organise a less messy transition and, in doing so, bring the equipment suppliers with them. The plan is to coordinate their efforts through a joint pilot line operated by companies who want 450mm production. They have yet to decide on a location or how the project will be managed but the chipmaking R&D centre in Albany, New York is the prime candidate right now. However, there will be other R&D locations. Intel's latest R&D fab is designed to handle 450nm wafers as is the new clean room at IMEC in Belgium. *