It takes complex processing to deposit a uniform layer of graphene on a wafer, then pattern a transistor structure on top

Graphene devices could speed comms

A new class of devices built using a special form of carbon could transform the communications industry.

Graphene. It’s a big deal. It must be, because it was the subject of the 2010 Nobel Prize. Prize winners Andre Geim and Konstantin Novoselov of the University of Manchester have pioneered our understanding of this carbon allotrope. Yet Geim is cautious about how long it will take for us to see advanced electronics applications, referring a little wearily to the idea of 'Graphenium Inside'.

For starters, in its normal state, graphene has no bandgap – and that effectively rules out even its medium-term use in digital circuitry, where a fairly sizeable bandgap is necessary to enable the high current on/off ratio necessary for a switch. That said, things could happen sooner for analogue and opto-electronic communications.

Graphene has properties that could help it turbo-boost RF and microwave chips. The US military is putting serious funding behind research into such applications through the Carbon Electronics for RF Applications programme run by the Defence Advanced Research Projects Agency (DARPA).

Hype vs reality

Even the most successful researchers emphasise that work is at a very early

stage. Techniques to create basic graphene field-effect transistors (FETs) have been demonstrated using variants of the mainstay CMOS semiconductor manufacturing process, most notably by IBM. Although the results are promising, they are also some way short of mass production.

The consensus is that graphene-based chips are unlikely to be seen in volume until semiconductors reach the 6nm process node, currently foreseen on the ITRS roadmap for 2024. Nevertheless, when graphene starts delivering its potential, it could be a real game changer.

Graphene is a two-dimensional, one-atom thick hexagonal lattice of carbon atoms, usually described as something that resembles chicken wire.

Its most valuable property for the communications industry is its high carrier mobility: its theoretical electron mobility is 200,000cm2/Vs, compared with silicon’s mobility of around 1,400cm2/Vs. Graphene also boasts constant optical absorption over a wide frequency range from far infra-red to near ultraviolet, and strong thermal and mechanical performance. Today, though, that mobility figure seems a distant target.

Device demo

At the recent International Electron Devices Meeting (IEDM), Phaedon Avouris, an IBM Fellow and lead of its nanoscale science and technology group, said his company has made graphene FETs on a silicon carbide wafer with a cut-off frequency, the point at which performance starts to seriously decline, of 170GHz. The comparable figure for present-day devices is around 40GHz. The work followed briskly on from IBM’s achievement of a device with a 100GHz cut-off, revealed only a few months earlier.

In addition to the performance, the other big advance in this work is IBM’s success in forming the graphene by heating the SiC CMOS-compatible wafers to 1,450°C. So far, devices have been made from separately produced graphene flakes and the material’s quality has been highly variable. Graphene also has a more planar structure than carbon nanotubes, which makes its integration into CMOS processes easier.

Nevertheless, as Avouris explained, once you get the graphene on the wafer, what follows is still tricky.

“To fabricate RF transistors, this continuous graphene layer is patterned by oxygen-plasma etching to electrically isolate the channel region, and source/drain electrodes are deposited by thermal metal evaporation.

“Top-gate stacks are formed by either depositing an organic seed layer - a nanofibrillated cellulose polymer,” he continued, “followed by hafnium-dioxide or aluminium-oxide atomic-layer deposition, or by plasma-enhanced chemical vapour deposition of a thin silicon-nitride film followed by a gate-metal deposition.”

Fabricating the graphene FETs also demands electron-beam lithography, a complex but CMOS-compatible technique.

Challenges

The challenges for IBM lie partly in the fact that while the achieved hole (positive charge carrier) mobility – at around 1,500 cm2/Vs – is high relative to the state of the art, it is still short of graphene’s potential. Similarly, the effective gate length for the transistors is comparatively large at 90nm, although much shorter than the 240nm reported in the research group’s previous announcement.

Avouris said the next step is to apply a self-aligned gate-fabrication technique that IBM has been developing. He adds: “We estimate that the RF performance and the cut-off frequency can be enhanced by a factor of two.”

This is groundbreaking work but also very much in pathfinder mode. This is even more the case for research under way in optoelectronics, where IBM is also pursuing graphene technology.

Building bandgaps

As for digital circuitry, the initial challenge here is the absence of a bandgap in graphene. For optoelectronics, there may be a way forward if a smaller bandgap than needed for, say, microprocessor circuitry, can be induced in the material. Avouris said his team has developed such a technique.

“One way to create a bandgap involves the application of a strong perpendicular electric field to AB-stacked, bi-layer graphene. These bi-layers have a four-atom unit cell, hyperbolic dispersion and no intrinsic bandgap. The low-energy bi-layer bandstructure involves two valence and two conduction bands,” he explained.

“The field produces an asymmetry by inducing charge transfer between the layers. The two atoms in the bi-layer unit cell that lie over each other are rather strongly coupled, so the resulting charge-transfer breaks the inversion symmetry and opens a bandgap.”

So far, this approach has been used to open bandgaps of 130meV and on/off ratios of 100 at room temperature and 1,000 for low temperatures. These metrics could, Avouris said, support applications such as terahertz emitters and detectors. More importantly, he sees scope to improve both the quality of the graphene and the dielectric that could bring bandgaps in the region of 400meV, suggesting still wider optoelectronics applications and perhaps paving the way for digital chips.

By basing its work on existing manufacturing techniques, IBM is showing that the semiconductor industry could eventually move to graphene-based designs. Some devices may emerge before 2024. The relatively small runs required for advanced military communications may mean that custom graphene chips get built before CMOS reaches the 6nm node. DARPA’s role in seeding and encouraging research says as much, as do suggestions that military uses may be viable once devices can be made with gate lengths of less than 50nm, where performance is the overwhelming driver. IBM’s success in reducing gate lengths so far may mean this point is reached relatively soon, although for the broader market other issues need to be addressed.

Terry Ma, vice president of engineering at design software vendor Synopsys, said at IEDM: “Emerging materials and technologies such as graphene and spintronics may require new approaches to modeling such as quantum transport and ab-initio methods.”

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