Segars and Hunter

Chip designers face double jeopardy at 20nm

Concerns are growing about the cost and time of the 20nm process generation due to go into production at the end of 2012.

The process technology is being hit with a massive increase in wafer-production costs coupled with fears that the expected 50 per cent increase in density might prove difficult to realise in practice. 

Historically, porting to successively smaller geometries has yielded big cost reductions as the doubling in chip capacity has outweighed a steady but much smaller rise in wafer-processing cost. 

Analyst firm International Business Strategies (IBS) projects a 60 per cent rise in wafer cost from 28nm to 20nm compared to a 20 per cent increase each generation from 90nm down to  28nm.

At the Design Automation Conference (DAC) in San Diego, Ana Hunter, Samsung Semiconductor’s vice president of foundry services, claimed: “We have got silicon results already.

“We are very confident with the base process being on time.”

Although the core process development is on schedule, many of the manufacturing changes make it harder to achieve dense circuit layouts.

Simon Segars, executive vice president of ARM’s physical design group, said: “The issues make you wonder whether it will be viable to port down to 20nm. 

“Ultimately we will get there. The question is when we get there, have we got something that’s useful?”

One of the biggest problems is the move to double-patterning for lithography. 

To make it feasible to offer a 50 per cent shrink in feature size, it will take two masks to define circuitry on each of the finest-geometry layers, reducing throughput in manufacturing and complicating design.

“Shapes have to be split and you have to be careful about how you draw the shapes. 

“Double patterning limits the degrees of freedom that you have as a designer and, potentially, you don’t get the scaling you wanted,” said Segars.

“But without double patterning, you cannot get the density in the first place,” said Hunter.

Philippe Magarshack, vice president of design automation at STMicroelectronics, said the complex interactions between design and manufacturing are having a knock-on effect on the timing of the 20nm introduction.

“We could spend the next five years optimising libraries and design rules to get the right performance trade-off. 

“But we have to stabilise them and get going because of the markets we are shooting for.”

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