Itanium server chips to get entirely new architecture for post 32-nm era.
Intel unveiled the essential features of its next generation server chips at the International Solid States Circuit Conference, its eight-core, 3.1bn-transistor ‘Poulson’ family. The new generation of Itanium processors – for which no release data has as yet been fixed – have a new, ground-up architecture that is intended to form the backbone for the company’s higher-end silicon for the next decade.
However, while it will take over from the McKinley architecture (unveiled in 2002), they will be fully compatible with the current 9300 Itanium series (aka ‘Tukwila’). The main reason for the radical architectural change was, Intel principal engineer Reid Riedlinger said, to develop something sufficiently robust to take Intel’s design programme sufficiently beyond the 32nm process node.
Other key innovations in the Poulson include a huge 54MB of on-die cache, with 32MB of last layer cache, and a ring-based system interface with potential bandwidth of 700GB/s.
“The core implements an 11-stage in-order, decoupled front-end and backend pipeline which employs replay and flush mechanisms versus the previous global stall micro-architecture. The decoupled pipelines enable an increase in resource utilisation and throughput,” the company reports.
The backend features six arithmetic logic units, two integer units, two floating-point units, two memory units and three branch units distributed across 12 ports.
The design uses core pair optimisation to compensate for variation as part of its power savings features. The chip can dynamically increase or decrease voltage and power in each core to improve frequency or recover power according to a sensor analysis of performance. Better and worse performing cores can then be matched. Thermal design power is 170W against 185W for Tukwila.
Further features are aimed at meeting RAS (reliability, availability and scalability) metrics demanded for commercial ‘mission critical’ uses.