Big Blue describes the hard work behind boosting today's frequencies
IBM’s record-breaking 5.2GHz zEnterprise microprocessor shows how difficult it now is to make gains in processor clock speed.
In a presentation to the International Solid State Circuits Conference, Jim Warnock, a distinguished engineer in the company’s System and Technology group, listed the various control settings that had been tweaked, together with a move to 45nm from 65nm, to ultimately get an increase on the zEnterprise’s previous generation.
At the local level, these included clock pulse width settings and their timings, the master clock failing edge delay, and local clock gating as well as the arrays and registers. At the global level, settings adjusted included clock duty cycle adjustment. Taken together, these steps provided just a 1.5% improvement.
“That was quite a bit of tuning to get the last bit out of the design,” he said.
Together with a process shrink, the overall improvement on the 65nm generation was 18%.
“There’s still room for future improvement, but things are getting harder and harder,” Warnock said.
The zEnterprise has four cores, 1.4 billion transistors and was manufactured on IBM’s 45nm silicon-on-insulator CMOS process.
“The chip has two additions compared to other IBM 45nm server [devices]. Two high performance wiring planes are added (13 levels in total) for solving critical resistance-capacitance issues and improving the L3 [cache] latency. Also, low threshold voltage devices are added for use on the most critical timing paths,” the company’s ISSCC paper says.
“The core microarchitecture leverages the 65nm design, but added the ability to execute instructions out of order.”
Various power techniques used on the design make it 25% more efficient than its predecessor.