Cadence

Cadence launches giga-flow

EDA vendor touts comprehensive silicon strategy at DesignCon

The launch provides further evidence of how the chip industry is looking to smooth the transition to the 28nm node over the course of 2011 by offering more comprehensive design infrastructure. There is always some user reticence when new nodes emerge and this is currently being exacerbated by fears that changes will incur increased engineering costs during a recession.

Based on Cadence’s existing Encounter platform, the flow is aimed at “giga-gate and gigahertz” designs and reflects the holistic approach it set out last year in its EDA360 tools strategy. It is ready for use at fabs run by both major foundry groups, TSMC and GlobalFoundries.

The flow has been developed in conjunction with a number of existing Cadence customers, including Global Unichip, a system-on-chip design house largely owned by TSMC.

“The 28nm process technology is both a great opportunity and challenge for designers, with its power, performance and area advantages coupled with challenges such as process variation and new manufacturing effects,” said Albert Li, the chipmaker’s director of Design and Development.

“Using the Cadence digital end-to-end flow, we are able to not only handle the complex routing, variability and manufacturing requirements of 28-nanometer designs, but also tackle 100m+ gate designs within a reasonable design cycle time.”

The flow is based on delivering unified digital design, implementation, and verification through techniques based on intent, abstraction, and convergence.

Features include silicon-proven 28nm rule intent (electrical, physical, DFM) with early, upfront tradeoff analysis, and a claimed 2x improvement in routing runtime through via and pin-density optimizations.

Early clock topology intent capture and planning uses physical information to optimise clock gating and balance clock trees throughout the design during synthesis. Data abstraction technologies enable entire blocks of logic to be modelled and optimized across logical and physical domains.

A physically aware pre-mask functional engineering change order capability automates implementation of functional ECOs and there is mixed-signal static timing analysis and timing-driven optimization to reduce iterations between analogue and digital design teams.

The flow also accounts for the shift to stacked chip 3D-ICs with capabilities spanning digital, full-custom, and package design, allowing them to be tuned according to performance, size, cost and power consumption.

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