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Jack Kilby with chalkboard

Flat beat

The recent International Electron Devices Meeting showed how chipmakers are striving to look to the future while having to innovate to preserve the present.

Fifty years ago, two engineers independently came up with ways of putting multiple transistors down onto one surface and wiring them together cheaply. These planar processes launched the semiconductor industry as we know it.

Ironically, the loser in the race to obtain a patent for the invention, Bob Noyce of Fairchild Semiconductors, offered a more manufacturable approach than his rival, Jack Kilby (above) of Texas Instruments. As a result, the business came to align behind Noyce's proposal. However, the early 1960s still saw a huge amount of frenzied research down many blind alleys until the industry settled on device structures that could be made so economically they provided the inspiration for Moore's Law.

The relentless shrinking of device features on the surface of a wafer now threatens the survival of the planar bulk-silicon transistor. The problems that cause most concern for process engineers is a direct consequence of the way that the transistor channel has become progressively shorter. There is a clutch of problems referred to as 'short-channel effects' but the industry's biggest headache is drain-induced barrier lowering (DIBL). Normally, when the transistor is turned off, there is a large potential barrier that stops electrons moving through the channel even if there is a reasonably high voltage between the main current-carrying source and the drain contacts that would otherwise push the carriers along.

Historically, there was plenty of space, in atomic terms, between the source and drain to maintain an effective barrier. In today's transistors, the heavily doped contacts are close enough for their electric fields to interact. This reduces the potential barrier that the gate is meant to maintain and allows electrons to flow. The resulting leakage current drains batteries.

'As conventional planar CMOS devices are scaled, the gate electrode begins to lose control of the channel,' says Injo Ok, a researcher with the Sematech think tank.

High-k metal gate stacks

One consequence of this was the move to high-k, metal-gate stacks, first by Intel and now by the major foundries. The silicon oxynitride gate insulator that manufacturers were using had gradually been thinned to provide sufficient control over the channel as it shortened. An unfortunate side-effect was that electrons began to tunnel through the steadily thinned insulator and leak away.

Chia-Hong Jia, director of SoC technology integration at chipmaker Intel, says: 'At 90nm, strained silicon compensated for the loss of oxide-thickness scaling. The high-k metal-gate (HKMG) introduced at 45nm recovered oxide-thickness scaling.'

The higher dielectric constant – 'k' for short – in the new metal-oxide materials make it possible to maintain a high electric field under the gate with a thicker, more electron-proof insulator.

HKMGs are harder and more expensive to make. Antun Domic, general manager of the implementation group at design tools group Synopsys, estimates that it adds 10 to 20 per cent to the process cost over conventional gate stacks based on silicon dioxide and polysilicon. This limits short-term use to high-end, high-power processors, such as those made by Intel. But as gate-control problems worsen, designers of mainstream and primarily low-power systems will have to look at HKMG or do something even more radical.

IBM has backed silicon-on-insulator (SOI) for many years. AMD's x86-compatible processors use the approach, which relies on the ability to use two wafers to create a silicon dioxide sandwich that insulates the silicon transistors from the bulk substrate. What puts many users off is the cost of the base wafer, even though it is a fraction of the total processed-wafer cost (Domic estimates the figure at roughly 5 per cent).

But the overall feeling is that change is inevitable because of how problems are piling up for planar transistors built on bulk-silicon wafers.

Jean-Marc Chery, CTO of chipmaker STMicroelectronics (ST), told analysts last year: 'The classic planar architecture will suffer from parasitic effects. The classic planar structure will not be sustainable beyond 20nm. We could keep a 2D transistor and use fully depleted SOI or move to a 3D transistor called the finFET. Each solution has a cost. Only a complete understanding of design, process and manufacture will allow us to make the right decision.'

FinFETs move the channel above the surface of the silicon wafer and allow the gate to wrap around it, providing more control than simply laying the gate against one side, as effectively happens now. The fin needs to be made very narrow to gain its full benefit, meaning that its width is less than that of the gate length, hitherto the smallest dimension on a processed wafer.

Making the fin is not as tough as it sounds because the techniques used to define gates – which depend heavily on optical interference – can be extended to draw the fins. Instead of building a fin by depositing doped silicon on the surface of the wafer, manufacturers will lay down blocks of material and then etch away the unwanted portions to reveal the structures. Etching is far easier to control in silicon-based processes than deposition.

FinFET drawbacks

One drawback is that the fins cannot yet be packed very closely together. Taiwanese foundry TSMC unveiled a design at December's International Electron Devices Meeting (IEDM) in San Francisco. It could, in principle, be used in its upcoming 28nm process but had a fin pitch of 50nm. Typically, the fins will be less than 20nm wide to ensure good gate control.

At last year's International Electronics Forum in Dresden, Jack Sun, vice-president of R&D at TSMC, said the company was working on developing finFETs but that a 'full release' would not come until the 14nm generation. Sun expects the finFET to scale down to 7 or 8nm. He was confident that the planar transistor would stay manufacturable down to 18nm.

FinFETs design is problematic, particularly for analogue circuits. Dick James of engineering analyst Chipworks says a transistor can be made wider by adding fins but that the width is thereby quantised. Analogue designers are used to designing transistors with arbitrary widths, so they will need to use different techniques. All design libraries will then need updating for finFETs but major tools and intellectual property suppliers are yet to start this.

Intel has hinted that it sees the finFET as an option although, like ST, it has not ruled out using planar transistors built on ultra-thin layers of insulator. These ultra-thin body (UTB) devices demonstrate much better gate control but are handicapped by poor mobility at normal operating temperatures. The on-state current is often ten times lower than for conventional CMOS transistors. Although off-state leakage is also much lower, the reduced on-current makes it hard to build fast, complex logic circuits.

Thomas Skotnicki, director of advanced devices at ST, argues that the drive strength only matters for high-performance designs, such as PC processors. He cites a decade-old study conducted by IBM that found that low-power transistors never use the full range of the transistor. What is far more important is enemy number one: DIBL.

'The average current reduces when DIBL increases,' says Skotnicki. 'It can reduce speed by as much as 20 per cent. In low-power design, that's a lot.'

For low-power and portable designs, Skotnicki argues the best strategy is to attack DIBL head-on. The best technology for that, he argues, is UTB SOI. FinFETs should also see lower DIBL but TSMC surprised delegates at IEDM when it showed results for its 20nm process that had higher than expected numbers. They were less than for bulk silicon but higher than the sub-100mV/V level normally expected of finFETs.

The choice between finFETs and UTB SOI is, for now, finely balanced. Skotnicki concedes that it will take some additional technical work to propel UTB devices ahead of finFETs. But the ultimate decision will depend on cost. None of the proposed approaches is cheap. SOI has the disadvantage of requiring different wafers. That may make it hard for high-volume players such as Intel to guarantee supplies, forcing them to consider finFETs even if the processed cost is slightly higher.

The problem for the silicon business is that few know how this will play out. In a vote at an IEDM panel organised by Applied Materials, most engineers admitted they did not know which way it would fall and the split between those who backed finFETs or SOI was even. Not since the invention of the integrated circuit has the future been so unclear.

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