A laser manufacturing a semiconductor

Making chips fit to print

Depositing the features on semiconductors is no easy task, and existing tools have reached their limit, says E&T.

As 2011 approaches, the major foundries are ramping up production on 28nm processes - making electronic devices with features so small they are stretching the capabilities of the equipment used to draw them to breaking point. To get to this stage over the past decade, chipmakers have applied an increasingly mindboggling array of optical trickery.

Lithography veteran Ken Rygler has likened the process to trying to paint a 1in line using a 3in brush. When he said that, the minimum feature size was just under 90nm and the wavelength of UV light was 248nm. Today, minimum feature size is below 30nm, although the wavelength has come down a little to 193nm.

The diffraction effects are intense. If you exposed the wafer using a mask that contained the desired transistor and wiring shapes, all you would get would be blurry, isolated blobs. Two particular techniques have kept the industry on track. Optical proximity correction (OPC) uses software to create many additional tiny features around the basic shapes. Phase-shift techniques use destructive interference to remove some of the worst effects of diffraction.

Because of modern lithography's reliance on interference effects, the easiest features you can print on a chip 'look like diffraction gratings', says Joe Sawicki, general manager of the Design-to-Silicon division at Mentor Graphics.

To help maximise the use of grating-like features, chipmakers such as Intel and Samsung are using a technique called double patterning. Here, the exposure is performed in two stages using two different masks. Intel deployed double patterning on its first 45nm processors. It chose the technique over immersion lithography, an alternative favoured by foundries like TSMC which uses the higher refractive index of water to improve effective resolution.

If you lay the chip out so that the lines used to form transistor gates run parallel to each other, you can maximise the diffraction grating effect. Mark Bohr, director of process architecture and integration at Intel, has described his company's double patterning technique as a 'draw and cut' operation where the lines are defined first and then cut using the second mask.

Even with double patterning, some shapes are hard to define. Sawicki says vias, which link two chip layers, are particularly problematic for any optical lithography process because 'they are inherently two dimensional and random in distribution, so they look nothing like diffraction gratings'. Double patterning demands two passes through a lithography tool - usually by far the most expensive item in a semiconductor fab.

For a typical fab throughput target of 100 wafers an hour, you need to double up these tools, significantly adding to the cost of moving to a new process. Mojy Chian, senior vice-president of Design Enablement at GlobalFoundries, told the Future Horizons International Electronics Forum: 'There are a lot of challenges in lithography and a lot of them are also cost based. The challenge is: how do we make it cost-effective?'

None of the lithography options for sub-25nm processes is particularly attractive. Jack Sun, chief technology officer and vice-president of engineering at TSMC, says the industry has absorbed a wafer-processing cost increase of 15 per cent each generation through better integration. 'But starting from 20nm it is going to be much more,' he continues. 'There are two major culprits. One is the transistor. As you scale down the pitch, the drive current drops, so you have to work much harder to maintain that. The other is the lithography,' says Sun.

As well as double patterning, Sun says TSMC is looking at extreme ultraviolet (EUV) and a wild card technology that may prove useful for foundries that need to run many different designs: maskless lithography using multiple electron beams.

Joël Hartmann, who heads Technology Development at STMicroelectronics, says: 'We have moved through 248nm to 193nm, and we are stuck. Below 20nm we are really expecting disruption. It could be EUV or maskless, which is attractive because it relieves the high cost of masks.'

Luc Van den hove, president of Belgian research institute IMEC, says: 'In lithography, our flagship programme is EUV. We believe it is the only technology that will be available for mass manufacture at 20nm and beyond. There will be others but we believe EUV is the only one with the momentum. It is a tremendous challenge but overall acceptance of the technology has increased a lot.'

EUV has been the favoured next-generation lithography system for more than ten years - but has never been in the situation where it can take over from optical lithography. It demands radical changes in infrastructure and, potentially, much more energy than existing equipment because of the problems in obtaining an intense, high-efficiency laser source.

Sawicki says Mentor has a development programme for EUV - but it still needs OPC. Using EUV for 20nm is similar in effect to using 193nm lithography for a 130nm process 'and you get mask-shadowing effects and flare that are way worse than with optical', he says, adding: 'I would be surprised to have many companies getting EUV at 20nm. It may come later in the lifecycle of that process. And I would still do a side bet on optical lithography after that. That said, memory manufacturers may push EUV harder.'

Van den hove argues: 'EUV will be expensive. But the main reason to go to EUV is because it is the technology with the lowest cost of ownership. However, only a limited number of companies will be able to afford it.'

Kurt Ronse, director of the advanced lithography programme at IMEC, says flash memory makers are likely to switch to EUV once they move below 20nm. 'It's very unlikely that EUV will be ready for 22nm NAND flash. Logic with a half pitch of 22nm, which most tend to call a 16nm process, will come later, maybe by 2016.'

Maskless lithography

The concept of maskless lithography has been waiting in the wings. The concept is simple, and is used in the manufacture of the masks that create today's chips. A robot defines a pattern by steering an electron-beam across the surface of a wafer. This is orders of magnitude slower than exposing the billions of features on a mask at once. Sun sees parallelism as a way round the problem.

'The concept is to have 13,000 beams all writing at once. For our multi e-beam programme, we are working closely with Mapper Technologies and we have already a pre-alpha tool. We are able to demonstrate its imaging capability with 110 beams, which will be upgraded to 13,000 beams later on. That can give you about 10 wafers per hour,' he says.

To get the throughput needed for volume manufacture, Sun proposes putting 10 e-beam machines in a cluster, with the machines made small enough to fit into the same footprint as an optical scanner.

'The industry is counting on this type of innovation to allow us to continue density scaling. We are investing to ensure disruptive capability,' Sun says.

Despite its problems, optical lithography has a chance courtesy of some advanced mathematics. Several years ago, IBM and Mentor agreed to work together on a source-mask optimisation, a technique that Intel refers to as computational lithography because of the volume of compute power.

Source-mask optimisation extends traditional OPC, using it, in effect, not just on the mask but on the light source. For a number of years, lithography tools have used more advanced lighting tricks such as off-axis illumination or multiple sources to deal with diffraction on the edges of features. Today, they use a few simple lighting shapes. Computational lithography raises the prospect of pixelated illumination where software defines a complex shape for the light source and creates OPC features on the mask that suit it.

'Rather than fragmenting and moving the edges of a target layer, this gives the optimisation engine complete freedom over the entire mask field. It can put features in areas that have nothing to do with what is printed on the chip,' says Sawicki. 'The mask can look bizarre, which leads to a problem. Building things that bizarre makes it very difficult for mask manufacturers to test.'

A significant component of mask manufacture, already in the millions of dollars per set, lies in testing and repair. With conventional OPC, it is hard to work out which features are correct and which are errors. To evaluate a mask that has no apparent connection to the final image demands advanced software that can simulate how the lighting will interact with the mask shapes.

The advantage that source-mask optimisation may have is that it could reduce the number of layers that undergo double patterning, according to Sun, which will help reduce manufacturing costs, although the price of masks is likely to increase.

Sawicki argues: 'With the combination of restrictive design rules, multipatterning, pixelated masks and steppers that are optimised to switch masks quickly, we could do optical for 10nm. It's down to the cost equation for each option.'

Recent articles

Info Message

Our sites use cookies to support some functionality, and to collect anonymous user data.

Learn more about IET cookies and how to control them

Close