Design for manufacture is moving to a new level of sophistication in the bid to keep Moore's Law on track.
Since the end of the 1990s, the semiconductor industry has worked on finding ever more sophisticated ways of drawing tinier and tinier features on the surface of silicon wafers. The wavelengths of light used can now be five times longer than the features themselves because it has proven too difficult and expensive to move from deep ultraviolet wavelengths - around 200nm long - to the extreme ultraviolet range.
Even in the late 1990s, feature sizes rapidly approached the wavelength commonly used in lithography - 248nm. As feature sizes get closer to the source wavelength, diffraction around the mask elements gets worse. The blurring caused by this diffraction threatened to distort the on-chip features or even make them disappear in some cases, rendering the integrated circuit (IC) unusable.
Engineering ingenuity came to the rescue in the form of optical proximity correction (OPC) - a technique that distorts the mask features, often adding extra elements to make the diffraction work for chipmakers instead of against them. As feature sizes have shrunk, OPC has become more complex and begun to affect how circuits are designed. Sometimes it is not possible to put certain shapes close to each other because of the optical interactions they will generate. Other shapes, however, can be brought much closer together.
Although the interactions are now shape-based, design rules and checks used to make sure those circuits are correct are always written using text and numbers.
We define features by describing in text how wide, tall and long they are. We define acceptable configurations by listing the distances that are allowed or required between features. This text-based, one-dimensional approach worked well enough for a while but words have finally begun to fail us. Some configurations or variants of a single configuration are so complex, they simply cannot be accurately or practically described with existing scripting languages.
It is not just lithography where these shape-based interactions come into play. The relative position of on-chip features can affect the performance of transistors. For example, a transistor will often be able to switch faster if it is not close to the isolation barrier that designers typically put around logic cells.
These performance effects expand the boundaries of influence within a design layout, so we now find ourselves trying to describe an increasing set of combined features that are all interdependent, and sometimes multi-dimensional.
At 45nm and below, checks literally explode in size as teams add more and more specifications and operations to each check to perform these multiple interdependent measurements. A lot of time and energy is expended trying to match the original intent of the rule and its implementation as a design-rule check (DRC) that will be used by a physical-verification tool. DRC runtime explodes, too, as more and more of these lengthy, complex checks are added to the rule deck.
Yet humans are predominantly visual animals. Even if we speak in different languages we can communicate basic ideas using pictographs. IC layouts are visual representations - any engineer who looks at a layout can recognise transistors and wires and vias as examples of patterns.
Pattern matching can let us return to using something more intuitive. Pattern-matching technology makes it possible to identify, isolate and define specific geometric configurations visually. Once recognised and defined, these patterns can be added to a pattern library that can be used by a pattern matching engine to automatically scan designs for matching patterns.
What, exactly, is a pattern? Patterns can represent configurations that are known to fail or negatively impact performance, and therefore should be removed from a design.
In the example image above, interference effects will cause a pinch or even a gap to form in the upper horizontal line in the region marked by the red square, but only if the line below ends somewhere between the two red lines.
Conversely, patterns can represent configurations that have been proven to be manufacturable, even though they may not fully comply with design rule or recommended rule requirements.
Once a particular pattern has been identified as prone to lithographic distortion and/or failure, pattern matching can be used during full-chip applications, such as place-and-route verification. By removing these configurations early in the design and implementation flow, designers can avoid the need to re-implement layouts after lithographic simulation.
With automated pattern matching technology, a visual pattern can be isolated and captured from a layout and directly converted to a formalised definition. This definition is stored in the pattern library, which is then made available to other tools, such as place-and-route and verification tools. Running a layout against the pattern library enables the design and verification teams to spot and remove any use of the patterns early in the design and verification process. Not only does pattern matching provide uniformity between the design, manufacturing, and test teams, but it also replaces lengthy design rules containing multiple operations with a simple visual pattern that is precise, exact and consistent across all processes.
Pattern matching is not a complete replacement for existing DRC methods, but an extension for checks with the highest level of complexity. Users will need to integrate this new capability into their existing physical verification flows in a gradual way as pattern libraries are built up. However, pattern matching does offer the promise of reversing the trend of runaway rule decks by providing an alternate, and far simpler, method of dealing with the most complex new checks required for advanced IC processes.
Mark Simmons and Jonathan Muirhead are technical marketing engineers for lithography friendly design and pattern matching in the design-to-silicon division of Mentor Graphics.