Xilinx opts for power reduction in TSMC process choice

TSMC is to be the lead foundry for Xilinx’s upcoming range of field-programmable gate arrays (FPGAs) built on a 28nm high-k, metal-gate process that will see the company use a unified architecture to underpin three different families of device.

As with previous generations, the Virtex family will occupy the top end of the series 7 FPGAs but it will be joined by Artix-7 as the successor to the older Spartan devices with the Kintex-7 devices occupying a new mid-range. With the split between Kintex and Virtex, the Virtex-7 devices will be focused mainly on larger telecom equipment and high-performance computing.

Vin Ratford, senior vice president of worldwide marketing and business development at Xilinx, said: “For people using Virtex-6 today, they can get half the cost and half the power by moving to Kintex-7.”

Ratford argued that the move to the 28nm process, which TSMC has tuned for lower leakage than its standard high-performance offering, has made it possible to cut power consumption across the board without sacrificing too much in the way of speed at the top end of the range. This, he said, would open up new markets for FPGAs, particularly in areas where makers of application-specific standard products (ASSPs) cannot afford to move from existing processes such as the mainstream 65 and 90nm technologies.

The company claimed that a 28nm-based FPGA will be able to deliver lower power in communications switches, taking an Interlaken switch as an example, than the equivalent ASSPs made using a 65nm process. Ratford said ASSP companies are unlikely to see sufficient volumes to make products such as these using 28nm processes because of the high engineering costs versus the expected volume.

“Historically, the biggest obstacles for FPGAs were power, price/performance and capacity,” said Ratford. “Lowering power allows us to increase usable performance and increase capacity.”

Giles Peckham, director of European marketing, said the company had worked on static, dynamic and I/O power consumption in the series 7 parts, using the low-leakage process, turning off unneeded parts of the memory and logic array, bringing in support for clock gating in the design tools and employing smart interface circuitry in I/O cells to turn off buffers when they are not needed.

“The biggest improvements we have made are in static power. The biggest decision we had to make up front was which variant [of the 28nm processes] we wanted to choose,” said Peckham.

Ratford addded: “It’s an obvious choice now but it wasn’t at the time. It delivers 5 to 10 per cent lower transistor toggle rate but reduces leakage power by up to 65 per cent.”

Peckham said an improvement to the way design tools handle partial reconfiguration can help save power as unconfigured portions of the die can be powered down if functions are loaded and unloaded periodically or swapped with other functions to allow the use of smaller FPGAs. “We have found partial reconfiguration has been used by customers to put more functionality into a single die but also is being used to reduce current consumption,” said Peckham.

Similarly, unused block memories can also be power gated. “And we have reduced the voltage of the configuration memories,” he added.

All of the first wave of 28nm parts from Xilinx will be fabricated by TSMC, although Samsung was also selected to be a manufacturer. “Samsung is still a foundry partner and we continue to evaluate them,” said Ratford.

As a member of the Common Platform programme, Samsung has a gate-first high-k metal-gate process rather than the gate-last manufacturing method used by TSMC. This will either demand a redesign for parts to be ported to its processes from the layout used by TSMC or the setting up of a gate-last process. “I think they will resolve it,” said Ratford but did not say which approach Samsung would choose: “That is their challenge.”

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