The need to incorporate analogue functions is slowing system-on-chip developments. E&T investigates.
Analogue circuits are holding back the development of the next generation of silicon for mobile devices, according to semiconductor executives speaking at two recent industry conferences. The problem is emerging as so-called system-on-chip (SoC) designs mop up more of the functions that, previously, would be divided across many chips on a printed circuit board. What used to be discrete chips are now realised as intellectual property (IP) cores that have to be incorporated into a larger SoC layout.
At the International Electronics Forum organised by Future Horizons, Hossein Yassaie, CEO of graphics IP supplier Imagination Technologies, said there is pent-up demand for the next process generation, which will see on-chip features scale down from 45nm or 40nm to 28nm. "A lot of people want to go to 28nm. But the analogue IP to let them do that is not available. So they will stay behind."
Doug Pattullo, director of technical support for TSMC Europe, said at the GSA & IET International Semiconductor Forum in London that integration is forcing what used to be digital logic-only SoCs to incorporate a growing number of analogue subsystems. Chipmakers are trying to put audio, power management and radio-frequency (RF) circuits on-chip.
"The TSMC wafer forecast shows mixed-signal and RF growing at 40 per cent. Over five years, we have seen a four-fold increase in the number of SoCs that have mixed-signal content, due to new designs in 90nm, 65nm and smaller geometries. Even today we are getting questions from customers who say they want to do analogue at 28nm," Patullo said.
Ciaran Whyte, co-founder and CTO of IC Mask Design, observed that for people moving to an advanced process node such as 28nm, "the analogue IP will always trail digital".
"A lot of our customers are primarily digital but their designs will have a lot of analogue components on them. The digital design progresses but the analogue portion delays tape-out or, when it comes back, turns out to cause failures. It's holding back SoC chips to a large extent," Whyte said, adding that the analogue blocks may be tiny. The company worked on one 65nm chip with just one analogue subsystem on it - a phase-locked loop (PLL) used to generate a clock signal. "That PLL held it back. But it was just 1 per cent of the die area."
The problem for early adopters is that, before the fabs have run significant numbers of wafers, the processes are not stable enough to produce models that accurately reflect how circuits will perform.
New design processes
One of the problems with migration to new processes, especially in the past few generations, is the need to lower the voltage. Voltage changes often force a redesign. Analogue designers have been busily dusting off old papers on architectures for common components such as amplifiers that were impractically big for older processes but which work well at the lower voltages that the new process technologies demand. But it takes time to generate working circuits that function well on a new process node, largely because the process is so manually intensive.
Paul Double, founder and managing director of EDA Solutions, says: "Analogue design parallels where we were with digital-logic design 20 years ago."
At that point, digital circuit design was computer-assisted but involved a lot of manual intervention. The rise of logic-synthesis tools, which generated circuits from a high-level written description, through the 1990s drove the use of automated place-and-route tools, which removed layout specialists who spent much of their time manipulating the physical shape of circuits - so-called "polygon pushing" - from all but high-end microprocessor design.
Design-automation companies have tried to introduce more sophisticated analogue-design tools. Whyte recalled that when he started design 15 years ago, Cadence Design Systems was bringing in its Virtuoso design environment. "They said that within a few years it would be completely automated. I thought: 'What a bad career choice'. Fifteen years later, I am still pushing polygons," he said.
"No-one has really taken a step back to ask: how can we do this quicker and better? But it has to move to more automation," said Whyte.
An increase in the number of previously obscure electrical effects made apparent by the reduction in size of transistors to the nanometre scale will help drive automation, said Double. Automatically-generated layouts will let designers try out more approaches that counteract the worst of these effects. "It's becoming more important to iterate designs, which puts more emphasis on the acceleration of the design process," he claimed.
Peter Frith, CTO of Wolfson Microelectronics, said the relative power consumption and die area of analogue and digital circuits in nanometre-scale processes drives the adoption of what he calls 'thick digital, thin analogue' designs. "The lowest power and noise analogue block is the one we leave out," he said.
Frith pointed to the changes in Wolfson's approach in recent years as audio decoders have become more sophisticated. It used to be more straightforward to mix audio signals in the analogue domain because the digital audio from different channels used different clock rates. Now, because digital signal processing cores can be made smaller than low-noise analogue circuits on advanced processes, it makes more sense to mix digitally.
"In the future, we will have every analogue input being digitised as soon as it enters the chip," said Frith.
Another option is to be less aggressive about the requirements of the analogue circuits. "We always have the problem of developing IP that is as good and as low-power as possible," said Double. "Maybe we have to take a small step back and accommodate, perhaps, a slightly larger die size and overdesign more to make the blocks more robust when they are put next to a noisy digital block."
Frith said for audio-rate signals, it's now possible to use the larger I/O transistors on deep submicron processes, which don't change as rapidly with each new generation as the core, high-speed devices.
The problems faced by SoC designers could prove to be an opportunity for European companies, many of which have specialised in analogue and mixed-signal design.
"There is a great opportunity here," said Pattullo. "This is one of the skills that Europe has. The question is how do we keep it there and get young engineers into the field? If we do, we can really increase the competitiveness of the region."