Vertical transistors could solve space problems as feature sizes on integrated circuits scale down.
When senior engineers from Intel go on the road to talk about their work, they want to leave you with one impression: the silicon business is not running out of steam. Physics may make it harder and harder to reduce the size of electronics circuits. But we are not near that point yet.
At the Design Automation and Test in Europe (DATE) conference in Dresden, Germany last month, George Bourianoff, one of the company's lead components researchers added his voice to the Intel argument.
'Scaling will continue,' Bourianoff stressed, but he added that the future will not be quite like past performance. 'Performance improvement will come from new materials and new structures.
'The next decade will be a time of unprecedented innovation for the industry, of necessity. It will have to introduce new things.'
Some of these changes have already happened. Although from the outside it looks as though most of the improvements in density and performance have come from just making onchip features smaller, there have been big changes in materials already.
Dimitri Antoniadis of the Massachusetts Institute of Technology (MIT) explained at DATE what really happened over the past ten years. Process engineers found they had the ability to draw finer and finer lines without having to change the wavelength of light they used. They took advantage of the way that lightwaves interfere with obstacles to work around the blurring caused by diffraction as feature size approaches the wavelength of the light itself.
The use of interference-based effects such as optical proximity correction and phase-shift masking has proved so successful in the past 15 years that the wavelength of light used in chip lithography has changed just once, and by less than 25 per cent, from 248nm to 193nm. Yet, in that time, minimum on-chip feature sizes have dropped from around 250nm to 30nm.
So successful were the early experiments with optical correction that the length of the transistor gate shrank quickly from the late 1990s. The name given to processes used to reflect this gate length but, as the gate was often made somewhat shorter, the everyday definition of 'process node', such as 0.18m or 65nm, shifted to a measure based on how far apart two transistors could be spaced.
The advantage that chipmakers achieved from making the gate smaller than anticipated came in performance. For a variety of reasons, smaller transistors can switch more quickly. This acceleration was seen in the market as a rapid rise in processor clock rate, which quickly moved into the gigahertz rate. And then it stopped.
'Somewhere around the 130nm was the limit of performance scaling commensurate with geometry,' says Antoniades. 'Since then, transistor characteristics have improved, but through the addition of new technologies such as strained silicon.'
Several years ago at the International Electron Device Meeting (IEDM), Antoniades and colleague Ali Khakifrooz pointed out that old assumptions about transistor performance do not hold in the sub-100nm domain. Parasitic capacitances, partly due to the way that electrical contacts either side squeeze ever more tightly against the gate electrode that controls the state of the transistor, sap performance as overall size reduces. And it was getting harder to shrink the gate because if it is made too short it simply leaks too much current.
The solution was to make it possible for the electrons to travel faster through the silicon channel under the gate. By straining the crystal lattice, either by adding atoms of the larger element germanium underneath or by putting layers of silicon nitride over the transistors to stretch the silicon beneath to match their lattice size, it is possible to lower the effective mass of the electrons. As the effective mass decreases, their maximum velocity increases.
'Many people said this couldn't be done: to introduce new materials and scale at the same time. But surely, it has been done,' says Bourianoff.
Antoniades says the addition of new materials has provided a boost: 'It is a remarkable increase in velocity that has allowed scaling to continue. Silicon left to its own devices could not have achieved this.'
There is bad news, however, Antoniades claims: 'We can't go much above where we are today. There are some tweaks that are possible but not much more. The parasitic capacitance is increasing. There is no more room for carrier-velocity improvement.'
What started with a mixture of silicon and germanium below the transistor channel may become a shift to germanium itself. The move would bring the electronics industry full-circle: the first transistors were based on germanium and not silicon.
What stopped the industry from using germanium before was the incredible match of the semiconductor silicon with the insulator silicon dioxide. The first germanium devices were bipolar transistors that used metal gates and contacts. But for the past 40 years, the semiconductor industry has primarily revolved around the metal-oxide semiconductor (MOS) transistor rather than more power-hungry bipolar devices. But there was no stable oxide of germanium and certainly not one that could match silicon dioxide's properties. So, germanium was forced to take a back seat.
The arrival of high-k gate dielectrics, kicked off by Intel with its 45nm process used on processors such as the Core Duo and the Atom, has made it possible to reconsider germanium. It is not so much the materials themselves, such as hafnium oxide, but the ability to build stable interfaces between crystals with such different compositions that has changed the way that process engineers look at these materials. There is no need to find a stable oxide of germanium - you can use something else entirely.
Germanium is not the only candidate. Elements from groups three and five of the periodic table, such as gallium and arsenic, which are used in radio-frequency devices, could supplant silicon, according to Antoniades. Intel has for some years worked with UK-based Qinetiq on other III/V combinations, such as indium and antimony. These materials, although difficult to work with, offer very high electron mobilities compared with silicon. As a result, they can support the higher carrier velocities that Antoniades sees as essential for coming generations of transistor.
There is a catch, however. Series resistance plays a part in determining the overall performance of a deep-submicron transistor. MIT carried out a benchmarking exercise on candidate materials and found that the III/V mixtures performed worse than silicon. The alloy indium gallium arsenide demonstrated a series resistance of 230m versus 80m for silicon, although the carrier velocity could prove to be double that of silicon.
'The performance of III/V materials could be better,' says Antoniades. 'But, at most, a factor of two.'
Heiki Riel, a scientist at IBM Research in Zurich, warns that, although III/V materials can provide benefits, such as better carrier mobility, other properties may also prove troublesome. 'With germanium and III/V, we have to be careful. Alternative materials may go in the wrong direction.'
A number of researchers working on future device structures believe that alternative materials offer the best chance of performance improvement under scaling if overall transistor design remains the same. The alternative is to investigate new shapes and structures.
Today's transistors suffer from a combination of issues that are lumped into the category 'short-channel effects'. One problem is that the drain electrode is so close to its opposite number, the source, that it lowers the barrier that stops electrons from passing through the transistor channel when supposedly switched off.
The gate itself winds up with limited control over the state of the transistor. Manufacturers have reacted to this by making the gate dielectric between the electrode and the channel thinner and thinner. But this has increased gate leakage, a further source of current loss, and become the primary reason for chipmakers such as Intel to move to high-k dielectric materials.
But the gate's control can be increased by having it act on more surfaces than just the top.
'By going to multigate devices, we can reduce the short-channel effects and reduce pressure on dielectric scaling,' says Riel.
IBM has championed the use of' silicon-on-insulator (SOI) processes as these make it possible to improve the control that the gate has over the channel by thinning the layer through which the carriers flow. The carriers cannot penetrate into the insulating layer underneath, so are forced into a thin channel that is nanometres thick. Controlling the thickness is a challenge as is mobility, although some simulations have indicated that ultra-thin body transistors can benefit from quantum-mechanical effects.
Variability - another problem for very small devices - improves with these devices according to researchers such Professor Asen Asenov of the University of Glasgow because there is no need to dope the channel with additives to improve electron flow.
Creating a raised channel so that a gate can wrap around three of the sides is troublesome but researchers have reported successes for a structure known as the finFET that uses a number of conventional manufacturing techniques to make extremely narrow transistor channels. The gate electrode wraps around thin fins, providing the additional electrostatic control needed.
Although originally envisages for SOI processes, recent research has demonstrated that it is possible to build the fins on conventional bulk-silicon wafers. The process is harder to control than on SOI but may improve with more work.
Riel looks even further into the future: 'The next step is to go to the ideal: the cylindrical architecture. Wrap your gate all of the way around the channel.'
Riel has calculated that, for a planar transistor with a gate on just one surface, the minimum gate length works out to be around 20nm to avoid the worst of the short-channel effects. With a cylindrical design, it's possible to reduce that minimum length to just 9nm. There is one further benefit of the cylindrical design: you can grow the wires vertically so that gate length becomes less of a factor in overall scaling.
The Zurich team has been able to grow silicon nanowires that have been doped with boron and phosphorus, to improve carrier mobility, up to 40nm in length on top of silicon wafers. The structures are comparatively primitive and exhibit very high parasitic resistance, but are workable.
Colleagues from IBM's laboratories in Yorktown, US explained at IEDM late last year an alternative approach they took to nanowire construction that may prove more fruitful. Riel says the minimum gate length on these wraparound transistors can be as low as 1.5 times the diameter of the wire.
'The all-around gate will be the ultimate scaled device,' Riel claims. She admits there are unsolved issues for integrating the nanowires with conventional processes. But these look to be easier to solve than issues with carbon nanotubes, which are often presented as being the next step from silicon MOS circuitry.
Bourianoff agrees: 'We think the ultimate limit for scaling silicon is the nanowire, although it's not going to be easy to introduce this at progressively reducing form factors.'
The evolution of the integrated circuit does not stop there - and an effective gate length of around 10nm stretches silicon scaling out to late in the coming decade - according to Bourianoff. Work is moving ahead on devices that use the spin state of the electron and other quantum-mechanical effects to operate as a switch.
'I want to counter the idea that semiconductor is a mature industry like steel or concrete,' says Bourianoff. 'We are entering a decade of innovation in the semiconductor industry. The industry really is an engine of innovation that will spin off new applications.'