Numonyx pushes phase-change writes past flash
Numonyx has pushed the write endurance of phase-change memory (PCM) devices to the point where it is now ten times that of typical flash memories and has launched a family of parts to replace DRAM and flash in embedded systems. The company is working on higher-capacity memories to go into future cellphone designs, agreeing to use the same interface as competitor Samsung.
Giuseppe Crisenza, vice president of strategic alliances for Numonyx, said the company has been optimising the technology on a 90nm process since it launched the first memories in late 2008. In that time, the write endurance increased from 100,000 to 1 million cycles.
Because flash memories have lower cycle counts they need to use techniques such as wear levelling to prevent overused bits rendering the devices useless. PCM devices have the further advantage of allowing individual bits to be written unlike flash memories that have to be erased in blocks and rewritten.
Numonyx will sell both serial- and parallel-interface versions of the 128Mb PCM, aiming mainly at the general embedded market rather than the mobile-phone business, although Crisenza said there are low-end mobile phones for the Asian market that could use the devices.
“There are a lot of applications that for cost reasons prefer the serial interface,” said Crisenza.
The SPI-based serial device will be able to function more like a traditional EEPROM memory, which only scaled up to densities of around 1Mb, with flash used for higher capacities. Although the devices will cost more than equivalent size flash memories, Crisenza said the overall system cost can come down because one PCM can replace a DRAM and NOR flash memory array in many embedded systems, perhaps sitting alongside a NAND flash for bulk data storage.
“There will not be a universal memory,” said Crisenza. “PCM can play between DRAM and NOR to reduce the overall cost, even if the device itself costs a little more. Very often, embedded device designers are looking for small DRAMs that aren’t available anymore or are costly devices so they have to use embedded DRAM. With this kind of device we can replace the embedded DRAM, E2 and code flash.”
As devices scale, Crisenza said the write endurance is likely to improve and that the manufacturing learning curve should also push the cycle count higher.
“When we come out with 1 or 2Gbit devices, there is no way to go serial. They will be parallel, high-speed interfaces,” said Crisenza.
“To speed up development we are jumping from 90nm to 45nm. Our goal is to provide samples of 1Gb at the end of this year to the main customers in wireless,” Crisenza added. “There will be two main devices, one that is a NOR replacement and the other will have a DDR2 interface. The specifications for this second one have been agreed with Samsung. Using a common specification will encourage customers to go with this solution.”