Transistor RAM looks up for DRAM replacement

Swiss startup Innovative Silicon has developed a one-transistor memory technology that the company claims can be made on conventional bulk-silicon wafers, instead of relying on more expensive silicon-on-insulator (SOI) processes, and which now hits the voltage limits needed for DDR3 and future DRAMs.

Mark-Eric Jones, president and CEO of ISi, said the company has produced test chips using the new form of the Z-RAM technology – which stores charge in the body of a transistor instead of a dedicated capacitor. He said the transistor is simpler to make than the long, thin capacitors needed for sub-40nm DRAMs although it uses a radically different design to the planar transistors used across the semiconductor industry today.

Although the company will not say how it lowered operating voltage to 1V and below – patents are currently being filed on the design – Jones explained that the design would work with processes beyond 30nm because the transistor is arranged so that the current through it flows vertically rather than horizontally. The gate electrodes are on the side, sandwiched between the contacts and the transistor body itself.

“What happens is that the minute you turn the transistor so that it is vertical, you can maintain a reasonable gate length without impacting the density of the memory,” said Jones. “You don’t have to shrink the stored charge so much as you scale the lithography. Effectively this is the advantage of a 3D structure. We can scale for decades before this runs out of steam.

“By shifting to the 3D vertical device, there is now no need for SOI and you can use just bulk silicon,” Jones added, which makes the structure compatible with the processes used in practically all DRAM fabs.

Typically, the vertical transistors are made before the logic and sense-amplifier transistors that complete a memory array.

“Basically we get this working with a DRAM process with very little change,” said Jones. For the test chip, developed with licensee Hynix Semiconductor, he added: “We didn’t even change the mask set for the planar ones much. You have to arrange a junction at the bottom and at the top, but this is all done before you build your normal transistors. It was surprisingly successful in that the first lot was functional, which does not happen often in this type of work.”

Jones said the voltage reduction has benefits beyond compatibility with DDR3 and later versions of the DRAM standard. “It also improves long-term reliability. With 1V we are now out in the region of 1015/1016 operations with no degradation."

Sungjoo Hong, vice president of DRAM at Hynix, said: “The advances in power and voltage demonstrated in our 54nm test chips show that the Z-RAM technology has solved the most challenging issues we have seen with floating-body memories. These results validate that the Z-RAM technology has great potential replace DRAM over the next few memory generations.”

Hynix and ISi have submitted a paper on the new design to the 2010 VLSI Technology Symposium, which takes place in June.

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