Tabula takes time for logic density boost

A Silicon Valley startup plans to use very rapid time-slicing to overcome the massive die area penalty that prevents programmable-logic devices from taking over from custom silicon chips.

Tabula has taken on a number of veterans from the field-programmable gate array (FPGA) and design-automation markets. Founded by former Simplex Solutions and Cadence Design Systems technologist Steve Teig (pictured), Tabula recruited Dennis Segers as CEO, who was responsible for the development of the Virtex family of FPGAs while at Xilinx.

The company’s ‘spacetime’ architecture uses reconfigurable computing techniques to switch logic circuits on the fly, using the same die area for up to eight layers of logic. However, Teig said the company has worked hard to “hide the revolution”, using tools to make the device look as though it is a virtual 3D chip.

“I believe spacetime is fundamental to the speed of computation,” Teig claimed. “For any technology that you might use to do computation it becomes cheaper to do reconfiguration locally than to send the signal somewhere else for computation. We’ve been trying to look 25 years ahead with this approach.

“At a certain point most devices will be spacetime because it will take less energy to reconfigure than to send the signal far away. This is the next wave of computing strategy,” he adds.

Within the architecture, strips of memory flank the logic elements, which are based around lookup tables, and the multiplexers that route signals between them. This is a subtle difference from a classic FPGA architecture, where a lot of the memory needed to hold state and temporary data is spread across the chip. With the Tabula architecture, much more of the state and data is stored in large blocks of static memory (SRAM).

Using those banks of state memory to feed configuration data into the programmable-logic elements, Tabula divides a raw clock signal of more than 1GHz into multiple sub-cycles – Tabula refers to these sub-cycles as folds. Each sub-cycle, the logic elements and multiplexers read out their state from the local memory, perform the computation and then move onto the next sub-cycle.

Signals still in flight at the end of each sub-cycle are caught by transparent latches, known as ‘time vias’, within the programmable-interconnect section and held until the next sub-cycle that needs those signals as inputs. Any logic behind the latch once it’s closed can be reused by independent logic on subsequent sub-cycles.

Teig explained it is easier to not think of the architecture as time-slicing but has a virtual third dimension: “For 99 per cent of my work I pretend the chip is 3D: it’s much easier to visualise the x, y and z axes rather than trying to visualise what comes into existence when, which just give you a headache.”

By taking advantage of faster transistors in future processes, Teig claimed Tabula can attain parity in terms of density with ASICs and application-specific standard products (ASSPs) within three process generations - at the current rate of development, that is just after the middle of the decade.

“We are trying to take ASIC as well as ASSP market share. We are positioning ourselves not to be the number-six FPGA company but to be a major player in semiconductors,” Teig said.

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