Design-kit standard attempts to remove Cadence lock-in

The group trying to break the stranglehold Cadence Design Systems has on the custom-design market through its Virtuoso suite of tools has released the first version of its open format for process design kits (PDKs).

The world’s largest foundry TSMC has given its backing to the Interoperable PDK Libraries (IPL) Alliance, which has as its members many of the electronic design automation (EDA) companies who compete with Cadence. The IPL standard addresses the problem that foundries have in delivering information about their processes that can be used by analogue and mixed-signal chip designers.

Historically, each EDA company has used its own format for holding process data. As a result, most foundries provide PDKs suitable for Virtuoso, which holds the highest market share for custom-chip layout, with a smattering of others.

By providing IPL-format PDKs, foundries can cut the number they support for advanced processes to just two – Cadence has, so far, refused to join the IPL Alliance. Both Virtuoso and the IPL standards are designed to work with the OpenAccess database format developed by Cadence and now maintained as an open standard by the Silicon Integration Initiative (SI2). The alliance’s plan is to donate IPL to SI2, said Oz Levia, vice president of marketing and business development at SpringSoft.

“Custom design gets easier as more standards participate in the game,” said Levia.

“With the open and interoperable PDK format, we expect to realise substantial cost savings in the development and support of TSMC PDKs, while delivering greater choice and advanced design features to our customers,” said Tom Quan, deputy director of design methodology and service marketing at TSMC.

The IPL 1.0 reference kit includes an iPDK developer’s guide, a sample 90nm reference PDK put together by Synopsys, a reference design and user guide. Ciranova, SpringSoft, Synopsys and TSMC led development of the kit. TSMC has developed an iPDK for its 65nm processes.

“The biggest driver is TSMC. In June last year they announced that will only support OpenAccess PDKs in the future for 40nm and below,” said Levia. “They are making good on that promise.

“I hope that this will open up a competitive market for more players to innovate and offer their technology. I think it will grow because there will be more automation. Before this, you had to get around the proprietary lock on the Skill code,” Levia added, referring to the language used by Virtuoso to automate aspects of layout creation, such as drawing inductors and other on-chip components.

IPL uses Python as its main scripting language for automation because it is an open standard. Cadence refuses to release the specification for Skill for use by other vendors.

Levia claimed a number of medium-sized integrated device manufacturers and large fabless companies are planning to use IPL, “especially the fabless companies that are large enough to have clout with foundries to have custom libraries. They are doing their own PDKs based around IPL”.

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