Custom logic to join programmable on 28nm devices
The rising cost of design and problems with power reduction will see programmable-logic supplier Altera move to a different way of implementing custom logic on its FPGAs.
The company will use the HardCopy system it devised to give system designers a cheaper alternative to using programmable logic in their systems to deploy applications-specific FPGAs and will, for the first time, let customers implement their own custom logic alongside the uncommitted arrays. The first outing for the combination will be a series of FPGAs made using TSMC’s 28nm process, which is slated to be ready by next year.
“Embedded HardCopy blocks will be a new way to improve density,” said David Greenfield, senior director of Altera’s HardCopy business unit. “We have used hard blocks in our architecture for more than ten years, implementing them using standard-cell technology. What we are doing in this generation is using HardCopy functions to get there. It lets us deliver different flavours of the products to customers that fit the needs of their applications.
“If there is a way for us to drop the cost of doing product variants, then it allows us to do more and provide more market-specific products,” Greenfield added.
FPGAs made using the 28nm will have strips of logic array designed for HardCopy alongside a larger fabric of fully programmable logic. Typically, logic implemented using the metal-programmed gate array area is ten times denser than that in the uncommitted array. Initially, Altera will use the HardCopy area to do its own market-specific products. “But it is envisioned that it will be available for customers to use as well,” said Greenfield.
“There are clear benefits in hardening functionality. When you compare an FPGA with an ASIC, there is a clear cost benefit for the ASIC. But the cost for all-layer design changes is expensive. What is different about HardCopy is that it is not a full standard-cell implementation,” Greenfield explained, adding that the mask-cost component is not as important in the equation as the cost of design, as the technique used by Altera is to translate an FPGA design into a hard-mask version rather than having the design team reimplement the logic using standard-cell ASIC tools.
For the 28nm-generation FPGAs, Altera will offer support for partial reconfiguration and will boost the performance of the serial transceivers to more than 25Gb/s to cope with an increase in the bandwidth of the communications designs that the company is aiming at with the upcoming family.