Toshiba inserts carbon for 20nm transistors

Toshiba says it has come up with a way to make transistor channels for future 20nm devices, providing a way forward for bulk CMOS technology.

The company unveiled the technology at the 2009 International Electron Devices Meeting (IEDM) held this week (8 December) in Baltimore, US. The technology adds carbon to the process to stop light atoms such as boron from diffusing into surrounding areas, which disrupts the channel-doping profile.

The technique works by forming three layers on the surface of the channel: epitaxial silicon (Si), carbon-doped silicon (Si:C), and boron-doped Si:C. The top epitaxial Si layer functions as a low resistance path for the electrons and the holes; the intermediate Si:C acts as a defensive layer to prevent impurity diffusion; and the bottom boron-doped Si:C layer suppresses the fixed charge caused by the Si:C layer formation.

Problems such as degradation in electron mobility in the channel area and variation in threshold voltage will become obvious at 20nm without changes to the manufacturing processes. These problems can be overcome, said Toshiba, by realising a steep impurity distribution in the channel area, a structure that requires a low impurity density surface layer and a high impurity density substrate layer. This structure contributes better gate electrode control over the low-resistance area on the surface by obtaining fine switching of the current.

Toshiba has confirmed that application of this novel structure achieves a boost in performance surpassing that of the conventional channel structure by 15 to 18 per cent.

Tosiba said previous R&D efforts have largely focused on nMOS transistors, in which channel impurities diffuse easily, or on examining the introduction of new solutions, such as SOI wafers and a 3D gate structure. Toshiba's new technology realises a high-performance 20nm generation process without employing such techniques but simply by optimising impurity materials and processes.

Arsenic has been confirmed as a potential candidate for the pMOS channel impurity. In the pMOS device, unwanted fixed charge accumulation in the gate insulator, due to the carbon in the Si:C layer, is resolved by adding a boron-doped silicon layer under the Si:C layer.

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