Test tool mines data for process troublemakers

Mentor Graphics has developed software to uncover faults in chip designs that cause yield problems in the fab by mining the data collected by wafer and circuit testers.

Tessent YieldInsight works by performing a number of statistical analyses on test data to try to uncover patterns in chip failures that may point to problems in the design itself. A growing proportion of manufacturing problems are caused by so-called ‘systematic’ yield loss in which a circuit that passes design-rule checks turns out to be more prone to fab problems than it should.

Following the company’s purchase of Logicvision, Mentor has brought all of its test product under the Tessent umbrella as it works to integrate built-in self test (BIST), Logicvision’s speciality, with Mentor’s own scan and test-compression software.

Joe Sawicki, vice president and general manager for the design-to-silicon division at Mentor, said: “We have been working for a couple of years now on this. We have been doing layout-aware diagnosis where, if you get a failure, the tool lets you know where something has gone wrong. Without it, you have to look at all the possible places where that fault could occur.”

Whereas the older tool focused on locating faults within devices using the results from a single test run, YieldInsight collects data from multiple lots to try to identify problems that are turning more often than they should but are not destroying yield.

“It comes back with statistically significant events that it finds so that you can do more effective yield learning over time,” said Sawicki.

Sawicki said much of the time series of wafers came back from test with a varying number of failed chips with no clear pattern. However, by subdividing the wafer into regions, such as the centre, the middle ring and the outer ring and into top and bottom zones, it is often possible to find systematic effects. For example, certain faults may cluster in the bottom half of the wafer around the outer edge perhaps because that is where the wafer is held by a deposition or etch tool.

“Traditionally, people start doing wafer maps to see where the failures are. If you squint a bit, maybe you can see some radial effect or something. But it is often very difficult,” Sawicki claimed.

By having the tool run statistical tests on different regions across multiple wafers or lots, it is possible to identify problems that cluster in one region.

“It’s not that YieldInsight finds things that you can’t find. It finds things that you will spend months figuring out,” Sawicki claimed.

Sawicki cited an example where vias had a tendency to fail on the lower edge of a series of wafers. However, the data was masked by problems that caused bigger, but short-lived yield excursions.

“They found when they took the samples into the lab, the problem started with a change in the etch recipe and were able to drive that problem out,” said Sawicki.

Recent articles

Info Message

Our sites use cookies to support some functionality, and to collect anonymous user data.

Learn more about IET cookies and how to control them