Grid powers simulation of future transistors

Grid computing has made it possible to perform large-scale simulation of transistor behaviour as devices scale below 30nm in length.

Carried out as part of the EPSRC-funded NanoCMOS project, a team led by Professor Asen Asenov of the University of Glasgow used Grid-based supercomputers to to simulate and analyse hundreds of thousands of 3D models to tease out their statistical variations.

The researchers said, due to the enormous complexity and computer requirements of such simulations, approaches were restricted to small statistical samples of approximately 100 transistors. This is insufficient to predict the tails of statistical distributions which are of tremendous importance for the overall reliability and yield of modern SoC products which need to be designed to accommodate standard deviations of six or seven sigma because of the sheer number of transistors on a single chip.

The simulations were carried out on widely distributed high performance computing clusters with thousands of processors, consuming more than 20 years of CPU time in a few weeks period, have revealed unknown details of the statistical behaviour of nano-CMOS transistors subjected to line edge roughness.

“The Nano CMOS Grid technology has helped not only to understand for the first time intimate details of the CMOS statistical variability, but also to develop statistically enhanced algorithms that will allow accurate prediction of statistical variability with greatly reduced computational efforts. This will be to the great benefit not only of the major semiconductor manufacturers but also to the vibrant UK design industry that is facing the increasing challenges of the modern nano CMOS technology and design,” said Asenov.

“The NanoCMOS project has pushed the envelope for large scale simulations and data management in the engineering domain. I am delighted that we have advanced the state of the art in understanding and modelling of statistical CMOS variability and helping to address the highest priorities facing the semiconductor industry” said Professor Richard Sinnott, the NanoCMOS e-Science director.

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