TSMC reworks design checks for 40nm and beyond

Taiwanese foundry TSMC has created a pair of data formats that it wants developers of electronic design tools to use when checking designs aimed at its 40nm and 28nm. Although work is still progressing on the formats, TSMC said it plans to license the format so that it is used more widely across the industry.

Mentor Graphics, which has the largest share of the market for design-checking tools with its Calibre product, has said its latest versions of Calibre nmDRC and nmLVS support the TSCM iDRC and iLVS formats, respectively. TSMC worked with several tool suppliers on the two formats.

Tom Quan, deputy director of design services at TSMC, explained the foundry’s aim with iDRC is to streamline the process of getting accurate design-rule checks into tools. “Conventional design rule files are getting very complex. It takes a lot of lines to describe the rules,” he said, adding that process variants add another dimension of complexity. By 2000, the process design kits supplied by TSMC had thousands of technology-description files needed to cover the different combinations of process variants.

Michael Buehler-Garcia, director of Mentor’s Calibre group, said the key advantage of iDRC is that it slashes the time it takes to convert hand-written rules into a form that is usable by a tool such as Calibre. Traditionally, design rules were comparatively simple, providing minimum gaps between transistor gates, for example.

In sub-90nm processes, the rules have become much more complex as the wider environment around a gate needs to be taken into account. In a 40nm or 45nm process, the distance from the edge of a standard cell, which usually is surrounded by a moat of polysilicon, has a direct effect on transistors even if they are in the middle of the cell.

Translating written descriptions of these rules supplied by the foundry into a machine-readable form takes time. “When it’s a hand-written document, we have to negotiate back and forth with TSMC to see if we have the correct definition of a rule,” said Buehler-Garcia.

The iDRC format aims to work around the issue by providing an application programming interface (API) to functions written by the foundry. The design-rule check tool analyses the layout and how it will appear on silicon, using calls through iDRC to find out whether the arrangement violates rules. The rules are defined using the Tool Control Language (TCL) widely supported by EDA software.

Quan said the use of iDRC would make it easier to communicate changes in design rules as a process ramps to production. “It makes it easier to apply new techniques faster,” he claimed. “The architecture is very modular and a little bit more readable.

Buehler-Garcia added: “Some customers will run a hundred designs through the fab over six quarters or so. Over that time, the process changes and you may want to adjust the rules. This platform allows it to happen. Also, at 28nm it is not just about process variability but the impact of design styles. One-size-fits-all design styles get harder to implement.”

The companion iLVS format for layout-versus-schematic checks will make it easier for users to implement custom devices, such as multigate transistors or pass-transistor structures, processes and have tools check them correctly. Buehler-Garcia said there is a heavy overhead with current rule deck structures.

John Ferguson, technical marketing director at Mentor, explained: “Normally they would have to get the full deck from TSMC and figure out how to plug into that. With iLVS, it is modular. It is much easier to add a new device in.”

Quan agreed: “The main impetus behind iLVS is to make it easier to program from a customer’s standpoint and make sure everything connects properly.”

Ferguson added: “LVS goes beyond just checking circuit integrity. There is also the post-layout simulation side, where you take parameters from the layout and feed them to Spice. Those parameters depend very much on the layout and how the devices interact with each other. With this, we get away from the situation where the customers or TSMC have to get into the guts of the tool.”

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