IBM and Soitec to work on 3D chips
Soitec and IBM are to work together on 3D integration technologies for 22nm and beyond, using wafer-bonding techniques applied so far by the wafer maker to silicon-on-insulator substrates.
The aim of the project is to develop cheap methods for wafer-to-wafer stacking. Soitec said it will use techniques based on oxide-to-oxide and metal-to-metal molecular bonding developed in collaboration with the French public laboratory CEA/Leti.
“This collaboration with Soitec is another step in IBM’s drive to accelerate 3D integration technology, and reinforces the expanding IBM ecosystem of leading companies and research organisations that are working together to achieve significant advances in semiconductor and packaging technology,” said Gary Patton, vice president of the semiconductor research and development centre at IBM. “Through these collaborations, IBM intends to accelerate the development of emerging 3D integration technology and demonstrate the possibilities of achieving higher circuit densities, faster speeds and lower power usage with this vertical integration approach.”