Chip designs: cheaper options

How can you get chips onto the market when you don't have an iPhone budget?

Since the late 1990s, people have complained bitterly about the rapidly rising cost of non-recurrent engineering (NRE) charges on chip designs and what would quickly become the biggest component of those charges: the amount of money needed to make a full set of layout masks. In little more than ten years, the price for a mask set went from tens of thousands of dollars through hundreds of thousands and now sits in the low millions.

However, when you take into account the software and hardware design and verification costs, even the amount of cash needed for a mask becomes practically insignificant. And then you have the problem of companies from different markets converging on a shrinking number of positions on the printed circuit board (PCB). You have to bet big and win big to not be faced with the situation of watching money go down the drain. It's a situation that has frightened venture capital companies away and made many in the industry wonder how new chip startups can get anywhere near enough funding to get to market.

As an integrated device manufacturer (IDM), Toshiba has made application-specific integrated circuits (ASICs) for customers for several decades but it is an industry in decline. At the recent GSA and IET International Semiconductor Forum, Aart de Geus, CEO of design-tools supplier Synopsys, has a vested interest in watching how many chip designs get done. The more there are, the more seat licences his company can sell. But the trend is not pointing up.

At the GSA/IET Forum, de Geus explained how Synopsys tracks the first 500 designs on each major semiconductor process node. "After 500, we stop counting," he said: that number is enough to indicate the trend.

"This has worked like clockwork until recently," de Geus claimed, with each node seeing the first 500 designs started typically within two years of the process going into production. That was the case for 65nm. In fact, the move to 65nm, according to industry insiders, went very well, with many companies skipping the 90nm process on the way from 130nm. But, for the 45nm and 40nm pair of nodes, the time to the first 500 is likely to slip to two-and-a-half years. For the upcoming 32nm and 28nm pairing, Synopsys reckons it will take three years.

Tatsuo Noguchi, technology executive for Toshiba, reckons: "Advanced processes, such as 65nm, carry a high risk of failure. Even more challenges and risks are coming to the fore. At 28nm, to go from concept to production will take more than $100m. Can any venture capital firm cover this? And, if yes, who can?

"The majority of fabless companies will definitely require a new model. The COT model can only be used by companies with huge operational teams. The majority will need a new model."

Fabless dilemma

Noguchi sees the COT model as being too burdensome even for those in the ASSP business to bear. "The fabless ASSP companies' core competencies are the architecture and functionality of their SoC products. But they are forced to use the COT model," he says. "They need to establish or outsource test and assembly, which carries risk, and invest in libraries and tools and a place-and-route infrastructure. But there is no differentiator in these functions."

Toshiba's plans to offer flows that are modelled on the traditional ASIC and COT approaches but provide options that let fabless companies use libraries and cores designed or migrated by the Japanese chipmaker to its processes. Companies opting for a more ASIC-like engagement will be able to provide their own IP blocks that will be incorporated into a chip by a Toshiba design centre at the place-and-route stage. Customers will hand off either RTL code or a netlist, with place-and-route performed by Toshiba. "The customer doesn't have to invest the EDA environment," says Noguchi.

With the hybrid models, the Toshiba offering will put the Japanese company into more direct competition with specialist design and operational support firms such as eSilicon, which use external foundries for manufacturing. Jack Harding, president and CEO of eSilicon, says moves such as Toshiba's reflect a need to use up fab capacity.

"Necessity is the mother of invention. If you have huge capital investments that are not used, you have to adjust your business model or even change it altogether to get that capacity consumed," says Harding. "With an overall slowing in the growth of the semiconductor industry, you will see a lot of behaviours change. They will manifest themselves in opportunistic business models and less long-term strategy."

Harding argues that the big problem for many companies that want custom chips is they simply do not do enough to keep up with changes in process technology and the operational issues of getting custom chips packaged and delivered. His argument is: why not let people who do those jobs every day do the work in exchange for a cut of the proceeds?

Other services companies, such as UK-based Sondrel will take on the physical design work and talk to the foundries, again sharing the investment in tools and design experience among a number of customers who still want designs done on leading-edge processes.

The rising cost of ASSPs on the more advanced process nodes was one reason why Altera, the number-two supplier of field-programmable gate arrays (FPGAs), reckons it can tempt some of those COT users over to its HardCopy programme. FPGAs are often too expensive to be used in high-volume designs because the freely programmable matrix of memory elements and wires that route signals from logic gate to logic gate on the FPGA take up so much space. On a die-area basis, an FPGA can be 20 times less dense than a hardwired ASIC.

Altera's answer with HardCopy was to convert the FPGA to a hardwired version. It replicates the basic structure of an FPGA but, by exchanging memory elements for metal links defined by a small set of masks, the die can be made several times smaller, bringing the die cost down to a point where, for medium-volume requirements, the lower NRE costs can swing in favour of HardCopy.

The problem with any chip that does not use a COT approach is that its per-unit cost will generally be higher. And any competitor with something close to the functions you are selling that ships in much higher volume can amortise the development across many more parts, allowing a lower average price. That does not mean you have to be locked out of the market: fast-moving companies able to piggyback on those high-volume designs can win.

Even in very high-volume products, the single-chip way is not always the one that customers pick. Joep van Beurden, CEO of CSR, says: "We think there are three value centres in the handset: application, baseband and connectivity, such as Bluetooth. Some companies claim to offer all three. That is an advantage but only if you are best in class in all three. No-one is going to to buy substandard connectivity just because the baseband is great."

Stan Boland, president and CEO of Icera Semiconductors, adds: "That is why you often see with a Qualcomm device a gadget chip, because the Qualcomm part doesn't do everything."

The gadget chip

Some suppliers are now pitching directly at the gadget-chip business. Xmos CEO James Foster says its multiprocessor devices can often beat FPGAs in terms of cost for communi-cations and I/O centric designs in consumer appliances.

Foster claims one customer plans to ship Xmos parts as standard products marked with its own logo and that the company expects to ship bare die that can be assembled with other devices as system-in-package (SiP) products.

"You can take a 65nm part with a 0.35µm analogue part, put them in one package and ship it as a product," said Foster. "We are not supplying bare die at the moment but we can do."

Foster reckons the NRE costs are a fraction of what it would take to implement the same functions on a comparable ASIC, with most of the design done in C. You can look upon the approach as an extension of the microcontroller market: the 4004 was a cheaper, programmable replacement for hardwired logic when it was specified for the Busicom calculator almost 40 years ago.

Paul Double, managing director of EDA Solutions, a company that provides access to a variety of low-cost mechanisms for manufacturing mixed-signal ASICs, such as multiproject wafers, reckons there are a lot of opportunities for companies to take off-the-shelf digital devices and processors and augment them with functions that are difficult to integrate. Because analogue circuitry does not benefit anywhere near as well from process scaling as digital, it often makes sense to implement mixed-signal devices on older processes.

The draw of older processes has seen foundries such as TSMC go back to technologies such as 130nm and offer versions that suit more specialised applications. Its latest move is to put laterally diffused transistors, which work well in radio power amplifiers, onto a new version of a 130nm process, expecting to trigger a new crop of mixed-signal applications.

It is worth looking at whether easing off on the relentless pursuit of scaling makes sense. Alternatives to deep-submicron chip design can massively reduce the capital investment, giving different opportunities.

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