XMOS cuts power and cost with process shrink

UK startup Xmos has tweaked the design of its multithreaded multiprocessor architecture to reduce its power consumption and introduced a single-core version to lower the entry point.

For the XS1-L1 and L2, the company has shifted from using a 90nm process to TSMC’s 65nm technology to reduce the die size and cost. In combination with the shrink, Xmos has taken the opportunity to implement power-saving modes that do not unnecessarily run the core processor when it has nothing to do.

The change means the new generation of parts, which includes a single and dual-core version, consumes more than five times less power when idle. A switchable phase-locked loop also lets threads slow the processor down when the system is lightly loaded.

With a single core, the L1 becomes the company’s entry-level processor, able to run up to eight hardware-scheduled threads.

Xmos CEO James Foster claimed the parts offer performance similar to dedicated hardware for typical interfacing tasks and can suit high-volume designs that need programmability better than field-programmable gate arrays (FPGAs).

Foster said one customer plans to ship Xmos parts as standard products marked with its own logo and that the company expects to ship bare die that can be assembled with other devices as system-in-package (SiP) products.

“You can take a 65nm part with a 0.35µm analogue part, put them in one package and ship it as a product,” said Foster. “We are not supplying bare die at the moment but we can do.”

Recent articles

Info Message

Our sites use cookies to support some functionality, and to collect anonymous user data.

Learn more about IET cookies and how to control them

Close