Toshiba tries to rewrite rules on ASIC and foundry production

Toshiba is attempting to rewrite the rulebook on ASIC and foundry manufacture by merging elements of both into a hybrid offering that the company claims is more suited to the needs of fabless chipmakers.

“We have looked into the future and asked: can a new ASIC model cover the new requirements?” said Tatsuo Noguchi, technology executive for Toshiba at this week’s (June 3) GSA and IET International Semiconductor Forum. “Would it provide advantages over the conventional COT [customer-owned tooling], foundry model?”

As an integrated device manufacturer (IDM) has made ASICs for customers for several decades but Toguchi pointed to market-research figures from Gartner that show an industry in decline. ASIC design starts, often from individual OEMs, have gradually been supplanted by application-specific standard parts (ASSPs) sold by fabless chipmakers to a number of OEMs.

“ASICs have been declining will decline even further,” said Toguchi. “The ASSP is taking over.”

Toguchi claimed the traditional ASIC model has proven to be too inflexible to accommodate companies wanting to sell ASSPs, but countered that the COT model is becoming too burdensome for smaller players to bear.

“The fabless ASSP companies’ core competencies are the architecture and functionality of their SoC products. But they are forced to use the COT model,” Toguchi claimed. “They need to establish or outsource test and assembly, which carries risk, and invest in libraries and tools and a place-and-route infrastructure. But there is no differentiator in these functions.”

Toguchi added: “Advanced processes, such as 65nm, carry a high risk of failure. Even more challenges and risks are coming to the fore. At 28nm, to go from concept to production will take more than $100m. Can any venture capital firm cover this? And, if yes, who can?

“The majority of fabless companies will definitely require a new model. The COT model can only be used by companies with huge operational teams. The majority will need a new model.”

Toshiba’s plan is to offer flows that are modelled on the traditional ASIC and COT approaches but provide options to customers that let fabless companies use libraries and cores designed or migrated by the Japanese chipmaker to its processes. Conversely, companies opting for a more ASIC-like engagement will be able to provide their own IP blocks that will incorporated into a chip by a Toshiba design centre at the place-and-route stage. Customers will hand off either RTL code or a netlist, with place-and-route performed by Toshiba.

“The customer doesn’t have to invest the EDA environment,” said Toguchi.

With the hybrid models, the Toshiba offering will put the Japanese company into more direct competition with specialist design and operational support firms such as eSilicon, which use external foundries for manufacturing. Jack Harding, president and CEO of eSilicon, said moves such as Toshiba’s reflect a need to use up fab capacity.

“Necessity is the mother of invention. If you have huge capital investments that are not utilised, you have to adjust your business model or even change it altogether to get that capacity consumed,” said Harding. “With an overall slowing in the growth of the semiconductor industry, you will see a lot of behaviours change. They will manifest themselves in opportunistic business models and less long-term strategy.”

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