Soitec gets ready for fully depleted SOI at 22nm

Soitec has said it is ready to start making 300mm wafers with ultra-thin silicon-on-insulator layers to support fully depleted transistors, which could go into production on 22nm processes.

The wafer manufacturer claimed it can make top silicon layers as thin as 20nm to a thickness uniformity tolerance of ±0.5nm in high volume.

FD SOI has been used commercially for many years, but mainly for niche applications. However, it could replace bulk silicon in mass-market chips as manufacturers try to overcome problems with variability with existing, strongly doped bulk-silicon transistor channels.

“On fully depleted SOI, we’ve demonstrated 25nm high-k metal-gate devices with matching characteristics far superior to those obtained on bulk silicon,” said Olivier Faynot, director of advanced SOI technology development at CEA-Leti. “As it eliminates the need to dope the channel region, FD SOI solves threshold voltage variability challenges at current and future nodes, while maintaining excellent Ion and Ioff characteristics and drastically reducing gate leakage current.”
“Ultra-thin SOI provides a solid foundation for planar and ultra-thin body devices, giving designers the ability to drastically cut power consumption and leakage while preserving performance. It simplifies the overall CMOS architecture, thus reducing the cost of ownership below a bulk approach,” claimed Paul Boudre, chief operating officer of Soitec.

Recent articles

Info Message

Our sites use cookies to support some functionality, and to collect anonymous user data.

Learn more about IET cookies and how to control them