ARM goes to low-run ASIC for at-speed multicore prototype
ARM has used a low-run ASIC production service in place of programmable logic or multiproject wafer runs to obtain prototype chips based on the Cortex-A9 MPCore multicore processor.
The UK-based processor designer used eASIC’s Nextreme service, claiming that it worked out cheaper than trying to fit the design across multiple field-programmable gate arrays (FPGAs).
“It could hold about two to three times the logic that the largest [Xilinx] Virtex5 could at the time and, therefore, for larger designs allowed the resulting speed to be significantly higher as we did not need to span the design across multiple devices,” said John Goodacre, director of programme management at ARM’s processor division.
The non-recurrent engineering (NRE) cost for the 90nm eASIC also compared favourably to the expense of purchasing multiple large FPGAs, Goodacre added.
Another option often used by ASIC and system-on-chip (SoC) design teams is to have the design placed on a multiproject wafer (MPW) through a conventional foundry. However, Goodacre pointed out that the NRE on the MPW approach would have cost more, as the project only needed a few devices, and would have taken longer to process through the fab.
“The eASIC device worked right first time on our PBX-A9 validation and development board,” added Goodacre. “We see the 90nm Nextreme eASIC technology as a very cost effective way of validating and demonstrating new products to our customer base and getting them to market much earlier.”
Jasbinder Bhoot, vice president of marketing at eASIC, claimed: “We see considerable interest from conventional ASSP companies and IP providers who see eASIC technology as a way of developing at-speed verification solutions that can even be taken into volume production. As process geometries shrink, eASIC will become one of the few practical solutions to perform at speed verification of IP cores and ASSPs.”