Running into the buffers

Exponentials never last forever. Sooner or later, silicon transistors are going to stop getting smaller, if only because it's tough to make one with less than an atom of silicon in it. The reality is that conventional silicon transistors will stop shrinking sometime before that happens. But how much sooner?

The end of the scaling of complementary metal-on-semiconductor (CMOS) silicon transistors could come as soon as a few generations from now.

IBM, Samsung and TSMC are working on 28nm processes that they expect to go into production next year. Intel should have 32nm this year with dimensions that are close to those of TSMC's 28nm process. Although it's not exactly easy to deal with, no one is expecting a catastrophe at that level. After that, you have the 22nm process which, in principle, should go into production in late 2011 or possibly 2012. There will probably be a 20nm or 18nm process that follows it. And then? It's anybody's guess.

Professor Andrew Kahng of the University of California at San Diego, among others, reckons getting beyond 22nm is going to be very tough indeed and possibly not worth the investment. Older watchers of the chip industry will not be all that surprised. Some 20 years ago, people warned that it would be impossible to cross the 1µm barrier. People now laugh about those predictions of doom and at the people who say some new limit is the end.

The International Technology Roadmap for Semiconductors has charts littered with little red boxes denoting things deemed necessary to put a future process into production but where there is no known way of doing it. But the industry keeps finding ways around problems, some of them quite bizarre and seemingly in contravention of the laws of physics. Take lithography, for example. You can get reasonably accurate 30nm lines out of 193nm lasers through careful lighting and interference patterns.

It's a $300bn industry that supports others adding up to trillions of dollars per year. It's not going down without a fight. But, even if scaling stops, it doesn't have to end there. It just has to find another way to deliver more transistors, or their equivalents, at lower cost.

The industry's ability to push 193nm lithography any further is running to its limit. Weird lighting techniques offer some respite but extreme ultraviolet lithography remains the most realistic option for getting into the 10nm range. And, 20 years on from when it was first mooted, it still doesn't work very well. And it doesn't look cheap.

Even if you could draw the transistors, are they worth having? "Variability will go from high to extreme," claimed Professor Jan Rabaey of the University of California at Berkeley at DATE.

"Most people believe 32nm is solved, but beyond that is pure crystal-ball gazing. There are many good reasons why CMOS may not scale below 22nm: energy; performance; cost; and size. Energy will still scale but it is slowing down and it will get harder to get energy per operation to scale. Cost per transistor will start to go up. There is a whole bunch of reasons why you can't squeeze transistors closer and closer together."

Power scaling

Processor makers and others depend on current trends in power scaling to improve performance. Increasing clock speed means a massive upward shift in power consumption. So, the smart answer is to use parallelism and run the processors a little slower. Conventional power scaling means that doubling the transistor count from generation to generation does not increase power consumption overall. However, it is getting harder to maintain that trend.

Because active energy scaling is flattening and leakage is increasing, overall power consumption could start to go in the wrong direction.

"Tricks such as concurrency may not be effective anymore. Simply using more cores and running them slower may not work," said Rabaey. "High-k dielectrics address it, but with the generation, leakage comes back at you."

"Active power versus performance trade-offs are becoming more important," says Jean-Christophe Vial, engineering manager at Infineon Technologies.

Rabaey claimed different approaches to building transistors could address the energy problem. However, these near- or sub-threshold devices are much slower than conventional transistors and much more susceptible to manufacturing variations.

The news is no better for memories. Samsung has been saying for a while that you just can't pack flash memories much more tightly together. They just interfere with each other. The pressure on DRAM has slackened in recent years as comparatively few people run 64bit operating systems that can use more than 4GB of memory effectively. Technical problems are not making it any easier to get cheap multi-gigabit DRAMs.

"I have long thought that 22nm would be where things get really tricky and expensive, and I have not seen anything that changes that view," Kahng claims.

Matthias Voigt, general manager of engineering at NEC Electronics in Europe, puts the break in Moore's Law later than Kahng:

"We believe that Moore's Law looks to be intact to 22nm and even to 18nm." But economic factors are already having an impact. He noted that fewer customers are moving to advanced nodes, such as the upcoming 32nm process. "The majority of designs today are at 130nm and 90nm. A few per cent of designs are looking for 32nm."

However, those users who do want the density of 32nm and smaller want it quicker than ever. The industry appears bent on running into a wall.

Vial says: "We think we will move to 28nm rather than 32nm. The only way to get sufficient scaling is to move to 28nm because we are on 40nm. We believe 28nm will be the next full node."

"Scaling does not continue as before. Area scaling is below average," Vial claims for the shift from one full process node to the next, in which linear dimensions drop by approximately the square root of two. "Only by using innovative architectures can we achieve the scaling benefit we need. But performance scaling from 40nm to 28nm is above average."

In effect, the last skip was of one-and-a-half process nodes, as TSMC decided that its primary process would be called 40nm, not 45nm as other silicon suppliers had done. TSMC claimed its 40nm was a shrink of approximately 10 per cent from its originally planned 45nm process. Ostensibly, this was to provide customers with a better reason for moving from the previous 65nm process.

Vial shows a series of SRAM designs which demonstrate a cell size of 0.06mm2 on 65nm, shrinking to 0.032mm2 on TSMC's 40nm process - a size reduction of 47 per cent. The 28nm cell, however, measures 0.0225mm² - a shrink of less than 30 per cent.

Limits on size

The problem is that process engineers are coming up against limits in how small they can make some of the features needed to build working transistors. And they are running into a growing list of things to slow down scaling.

Ten years ago, the sidewalls and spacers that were introduced to make it possible to dope and treat transistor gates so they could conduct electricity effectively were tiny in comparison to the gaps between transistors.

Spacers, for example, are used during manufacture to selectively dope the parts of the channel closest to the drain and source contacts. These regions of high doping are needed to control leakage - without them, the transistor would never turn off properly.

And, during that time, engineers were reasonably free to regard gate length as being independent from gate pitch, as the pitch dimension was generally considerably larger. That is no longer the case.

Bala Haran of IBM Research explained at last year's International Electron Device Meeting (IEDM) that it's hard to find space to form contacts between the transistors and their connecting circuitry: "With previous [process] nodes, we had the luxury of not scaling the length because we had sufficient space to land the contacts. The gates are now in such a tight space that we have no space to land the contacts."

For the anticipated design rules of a future 22nm process, the gate has to be 25nm or shorter, according to Haran. A further problem, he says, is that scaling the contact itself is tough because yield suffers. "As you shrink, you start losing vias," he explained.

Stacking chips

If the industry is pushing against economic and technical limits, what can it do? It can go up. The idea of stacking chips on top of each other is far from new. The iPhone has plenty of those modules inside. However, if it is the only realistic way to improve density without increasing cost, that knowledge will push companies into making stacks cheaper to build and test. It will also change architecture. Right now, architects pack as much memory as they can onto the same chip as the processors knowing that the requirements for memory and logic in a silicon process can be quite different. With stacks, they don't have that limitation. You can have a chip optimised for memory and one for logic and just glue them together.

It's not Moore's Law as we know it, but it would not be the first time that the underlying assumptions of the law have changed to accommodate a market expectation - and that is what the law has come to signify - of a doubling in density every two years at equivalent end cost.

That 1µm barrier did not pass without anyone noticing: the metrics that gave us the doubling after that point changed from those that drove the law before it. The changes that came around the start of the 1990s displaced the Japanese from their recently won supremacy - they distrusted one of the technologies needed to push scaling forward and US-owned companies won back a large chunk of the chip business.

A few years after the 1µm point, chip size stopped growing - at least in mass-market parts - because increasing the die size proved uneconomic. But the 1975 version of Moore's Law assumed that chip size would grow consistently. The industry made up for the shortfall by working harder to shrink 2D features and add metal layers - the first phase of expansion into 3D. Now, we are hitting the limit of that 2D shrink strategy. Unless there are some dramatic changes in technology, the third dimension looks to be the least costly. And Moore's Law is likely to win another reprieve.

Recent articles

Info Message

Our sites use cookies to support some functionality, and to collect anonymous user data.

Learn more about IET cookies and how to control them

Close