Breaking up is hard to do

Vertical integration seems so 20th century. However, it could be making a comeback, finds E&T.

Chip design has never been that easy, no matter how certain eras or process nodes might appear in retrospect. There has always been a tension between what physics could offer at any one time and what the tools, intellectual property (IP) and engineers could do to exploit it.

If there is a way in which the challenges facing present-day semiconductor development differ from the past, it is in the level, breadth and thereby the complexity of the integration. A system-on-chip is a sensitive combination of different hardware blocks, processor cores interconnect and embedded software. Pulling all this together is, quite simply, horrible. The other thing you can be sure of on that list is that something has been missed out.

The task then presents substantial methodological challenges. It requires an abstraction of the design flow up to what the industry calls the electronic system level (ESL). This is a confusing term, given that it refers largely to generating designs on a modular basis with some confidence that the various blocks will work together when implemented across billions of gates in a single chip - a single chip that was once a plethora of components scattered across a printed circuit board (PCB), which itself is also still referred to as a 'system design'. See the problem?

The main technological contrast here, though, is that the 65nm node to which a growing number of teams are moving is prone to considerable manufacturing variation at the gate level. Meanwhile, what the lithography might have printed with acceptable regularity at one node will not necessarily go for the next. In this context, a fine-grained understanding of design-for-manufacture (DFM) is necessary, so that design features work, and designers understand where redundancy may be possible or necessary.

All this means that design costs are skyrocketing. Yankin Tanurhan, vice president and general manager of non-volatile memory-IP supplier Virage Logic, told the 2009 Design Automation and Test in Europe (DATE) conference that a fairly typical design can today cost $50m to $70m, about 12 times as much as a decade ago. "It's a price tag that's very hard to pay on your own," he said.

As a result, chip design companies are turning to a network of service suppliers. Speaking alongside Tanurhan, Denis Audoly, director at Wipro Technologies, a specialist in wireless IP, said that these suppliers mainly fall into five categories: design services, IP, electronic design automation (EDA) software, foundry, and packaging/test.

There is frequent overlap between these categories, and this points towards perhaps the main business tension in semiconductors today. To control costs so that it can direct the greater part of its resources towards the differentiated part of its design and then get its chip to market as quickly as possible, a fabless semiconductor company is typically looking to deal with as few vendors as possible - the one-stop solution makes a lot of commercial sense. As a result, there is the chance for one of the five supplier groups to dominate the others and begin to act as the chip design market's gatekeeper. After a period of disaggregation into 'small fish', there is the possibility that a new behemoth will emerge and control the business.

The suppliers treat this particular point with some caution. On one hand, as Wally Rhines, chairman and CEO of EDA vendor Mentor Graphics, noted at DATE, such an integrator plays a necessary role. "The customer will always want somebody to make the process of buying and choosing third party tools as simple as possible," he told E&T. Rhines also accepted that the foundries may be, today, best placed to fulfil that role in many cases.

Certainly, in a still hardware-dominated business, the fabless companies themselves set a lot of store in their foundry's advice. Trevor Robinson, CTO of Desix Technology, a specialist in RF and mixed-signal design, said that as the industry moves to ever smaller process geometries, particularly beyond 65nm, the manufacturing partner inevitably plays a greater role.

"We are ultimately tied on our [EDA] tool choice, for example, to what the foundries provide," said Robinson. "In our case, analogue design is particularly closely tied to the physical properties of silicon and therefore very sensitive to any variation in manufacturing. But, even in the wider sense, the foundries are driving and dictating tool choice to a much larger extent."

During DATE itself, Taiwan Semiconductor Manufacturing (TSMC), the world's largest foundry, announced a service that underlined Robinson's point. Already, TSMC has offered Reference Flow, a regularly updated catalogue of tools approved for its production processes. Rival foundries such as the Common Platform - an alliance between IBM, Samsung and Chartered Semiconductor Manufacturing - and UMC have long done much the same. Customers demand such guarantees. That's just a fact of life. The new offering nevertheless goes a little further.

Pre-qualified toolsets

"Integrated Sign-Off Flow (ISOF) is an automated RTL-to-GDSII chip implementation flow that tightly integrates all process-specific items including pre-qualified library and IP, selected EDA tools, production-quality flow, advanced design methodology, and TSMC foundry technology files that have been proven and refined over hundreds of applications," said the announcement. "With embedded TSMC design know-how and sign-off recommen-dations, the new flow uses pre-qualified EDA toolsets from multiple vendors and leverages industry-proven TSMC Reference Flow methodology."

What does 'pre-qualified' mean? TSMC is not saying that there is only one 'approved' way to design a chip so that it will be fully manufacturable. There are still various options within ISOF from various vendors. However, Jean-Christophe Lonchampt, the company's director for marketing and business development in Europe, acknowledges that it is also more "specific" than earlier recommendations.

"We have customers who just want to pick a design flow and get started," he told E&T. "That is not such a surprise now. Many fabless companies are very cautious with money because of the world economy - and it is more the smaller players who want you to help them make these choices. Also, there are pressures towards delivering designs on time. We have to respond to those."

Even Lonchampt, though, is careful to qualify just how much power this gives TSMC and to what degree its position as integrator is a power play as opposed to a natural market position as more and more manufacturing is outsourced. For example, he explicitly rejects the idea that TSMC will get actively involved in corporate venturing outside the production arena - its investments will be in its existing strengths rather than in expanding into those of its fellow chip design suppliers.

Wipro's Audoly also points out that, in practical terms, the opportunities for a single company to disaggregate surrounding parts of the supply chain is difficult, citing technology complexity, the impossibility of gathering all the talent needed to secure unchallenged leadership in that technology, today's cost constraints and market deadlines, and finally - and perhaps most tellingly - "political games".

"Even if a company has a lot of good people normally [this kind of integration] doesn't work because of how companies function internally," said Audoly.

Mentor's Rhines, though, offers a still more pragmatic reason why over-dominance by one third-party supplier could become a weakness rather than a strength, if it ultimately serves to isolate that company from innovation.

"Everything costs a lot to develop so everybody has to partner," he said. "You have reached the point where no one can do it alone - or maybe only one company can, but it [Intel] has suppliers too. That goes as much for the foundries as anyone else."

Rhines cites an example involving his own company and IBM. "When I started in this business, all the big companies did everything themselves, and IBM would be one of the big examples of this. Today, it's nothing like that and we're allied with IBM specifically on computational lithography. It's a technology we need for the industry to progress, but also one that no one company can take forward on its own."

A game of partnerships

So, the need to innovate may well force companies across chip design to play nice. Indeed, it is hard to find a branch of that business now where almost any top level form of R&D takes place on a wholly internal basis. Costs have forced everything to become a game of partnerships where you have to acknowledge the other guy's commercial position. However, privately, some executives say disaggregation should still remain on the agenda.

The issue here is, as is so often the case, the state of the world economy. If things are that bad, customers might well settle for something that is not as polished, not as technologically perfect as may be possible, and go with the cheap, off-the-shelf solution. Chip design actually leaves very little wiggle room for plunging downmarket quite so easily, but if things get really bad, thinking goes, who knows what might happen. It is, even among its proponents, not the most likely scenario - but, while the recession persists, nor is it impossible.

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