Head to head

Altera and Xilinx are limbering up for their next bout for the top of the programmable-logic market.

If one thing characterises the FPGA industry, it is sudden reversals of fortune. The two market leaders fight tooth and nail for supremacy and at the moment Xilinx, the first company to launch an FPGA, is at the top of an industry it helped define. Rival Altera battles to overtake them, as the companies joust over differences in architecture and what an FPGA should contain. But over the 20 or more years that the companies have competed, the roles have been reversed, due to bad luck or poor judgement on the part of one or the other.

A lot of the battle has been about being able to access and apply the latest manufacturing processes. At 65nm, Altera was in the back seat. Having carefully planned an architecture that would deal with rising leakage power, the company was unable to launch high-end Stratix parts until early 2008. Although TSMC was ready with a 65nm process much earlier, and market share figures indicate that the company was able to pull ahead of its competition, most of the running was made with the low-power version of the 65nm process (65LP).

Although 65LP suited Altera's cheaper Cyclone family of FPGAs, it ran too slowly to support the Stratix parts, which had to wait for the higher-power 'general purpose' process (65G) to enter production. Altera was left unable to ship a key product line. Now, the shoe is on the other foot. Altera's Stratix 4, based on TSMC's 40nm G process, is following hot on the heels of the 65nm-based Stratix 3. The first part, the GX230, started sampling late last year while Xilinx kept quiet on its plans for 45nm.

David Greenfield, senior director of product marketing for high-end FPGA products at Altera, boasts: "We said back in May we were going to ship this part by the end of the year. And we have done what we said we were going to do.

"A lot has been down to the partnership with TSMC. We are not TSMC's biggest customer, but probably the most important for process development. This is the first product working and shipping on the high-performance [40G] process."

The situation did not look good for Xilinx as one of its primary suppliers, UMC, appeared to be trailing fellow Taiwanese foundry TSMC with a 45nm or 40nm process. Although UMC claimed to have produced working SRAMs based on a 45nm process in late 2006, little more was heard until two years later, when it said it would introduce a high-k, metal-gate process at 45nm. This was a move that TSMC and the Common Platform partners decided to put off until the 32nm node.

Xilinx says that it is now sampling low-cost Spartan-6 products on UMC's 45nm, 9-metal-layer , dual-oxide process, and will introduce production volumes in the second quarter of this year. UMC's tardiness appears to have cost it dear, though. The Virtex 6 parts will be built on a 40nm, 12-metal-layer, triple-oxide process by Samsung, a member of the Common Platform Alliance. Samples are due in the second quarter.

Although Moshe Gavrielov, CEO of Xilinx, says he wants to get away from discussions of the 'bits and bytes' of process nodes, it's clear that the company has decided to spread its risk by adding Samsung as a foundry: "We have a dominant market position at 65nm and it was achieved with UMC. I believe we will have a good position now with UMC and Samsung. Using Samsung gets us to the Common Platform, which is one of its attractions."

Altera is now planning for the shift to 32nm, as well as rolling out the remainder of the 40nm. However, both companies are weighing up a slowdown in the shift to new processes.

Gavrielov rejects the idea that the combination of the current recession and Xilinx's late start with 40nm and 45nm parts means it won't have much time to sell premium parts before rival Altera moves ahead to 32nm: "I am convinced we'll sell a lot on 45nm. Due to the nature of the businesses we are in, products take three years from introduction to significant revenues of $50m/quarter, and then tend to have at least a five to seven year useful lifespan."

He also expects UMC to come up with a 32nm process, despite carrying the development costs alone "and you can bet your bottom dollar we're already designing our next generation of products [to use it]."

Market-specific approaches

Greenfield argues that the value of a process is not the same for the whole product line: "Today, it is very much about market-specific approaches and figuring out what the specific requirements are for our customers. It means using the right process to address these needs. Even though we are at 40nm, we will roll out new families at 65nm. And we may use LP processes at other process nodes for certain product families."

Greenfield adds that shifting to newer processes always presents risks: "What is interesting about processes is that the process we are on now seems great, the next seems manageable and the one after that is rolling off a cliff."

It does not signal a slowdown. "For us, the next process looks great. Having a leadership position provides an incredible value proposition. It is working for us. So we will get as close to aligning with the first process that we can. That will be for the high-performance, high-density segment. But that may not follow everywhere."

Although TSMC has indicated that it is prepared to use a high-k, metal-gate process on its upcoming 32nm node, Altera is not ready to commit. "It adds capabilities that are important to us. But, whichever process gives us high performance, low power and the lowest cost possible, we will align with that," says Greenfield.

Neither the 40nm or 45nm processes that Xilinx has committed to use high-k dielectrics, but it might come in the 32nm processes they use: "When you go beyond 40nm and 45nm, high-k becomes more appealing and has the potential to be more mainstream. The IBM [Common Platform] alliance has touted its use, and I think ARM is supporting it too." Beyond process, one of the key battlegrounds for Altera and Xilinx is over how the FPGA communicates with the rest of the system and, indeed, whether they become the entire system. As FPGAs are strong in the communications sector, both companies have put a growing number of serial transceivers on their high-end devices. However, the speed of those interfaces has not risen as fast as the underlying processes have scaled. For a while, Xilinx's serial transceiver speeds went into reverse. That now seems to have been rectified with transceivers in the top end of the Virtex-6 range that are designed to run at 11.2Gb/s.

Xilinx sees the Virtex parts absorbing the functions of processors, previous-generation FPGAs and I/O in major systems such as 3G-LTE basestations and even in optical routers for the core network: the 11.2Gbit/s transceiver specification gives the Virtex parts enough headroom to implement OTU-4 framing and forward error correction in optical networks. Xilinx says its largest Virtex part can support total bandwidths of more than 1Tb/s, though whether it can do anything useful with that much data remains to be seen. There's also the issue of successful implementation to be overcome.

Serial transceivers

Recognising the importance of serial transceivers, Greenfield claims Altera took special care to make sure the company could get them to work on the 40nm process. "We did a test chip of a single-channel transceiver. It came out in the first quarter and gave us an incredible vehicle for process analysis. And we found some things we didn't expect.

"We wanted to reuse a lot of the technology from Stratix 3 in Stratix 4. But we found we couldn't use as much as we intended. But to do it with a test chip showed what we could do and what we couldn't," argues Greenfield, reinforcing a view at the company that early test chips are vital for bringing on any new process.

A key discussion is over how much of the system the FPGA can expect to consume, which begs the question of whether the programmable devices need to incorporate more hard IP to prevent costs ballooning if they absorb host processors. Altera launched products at the start of the decade that included hardwired processors but quickly withdrew. Xilinx laboured for longer with the PowerPC but these processors were often used more as super-state machines than host processors. Is the market ready for a change?

"Most very large ASICs have processors in them. As our FPGAs become larger and larger and become the hearts of systems, having some kind of processor support is clearly going to be important. But there are still many, many of our customers who have central processors sitting next to the FPGA and that will continue," says Greenfield.

"When we started in the processor space, we thought we would replace processors over time. I don't think we have that grandiose vision anymore," Greenfield concedes.

Xilinx has made great play in this announcement of a 'pyramid' of useful stuff to go with the chips, with at its base general design tools, simple IP, base boards and reference designs. Next up the hierarchy are domain-specific tools, IP and reference designs, followed by market-specific IP and software, with the customer design at the pinnacle. Xilinx IP is clearly a very important part of this strategy, but Gavrielov was cagey about whether Xilinx would licence critical processor cores, such as those by ARM and MIPS, and the PPC.

Asked whether the company could develop as it wishes to in the communications market without an ARM core, Gavrielov said: "There are a number of architectures with different footprints [in the communications sector] and ARM has the biggest footprint. In high-end consumer applications, MIPS and PPC dominate. These are the three prevalent solutions."

Gavrielov wouldn't go further, other than to say that the real issue was between implementing hard cores and soft cores, and that the company would be updating it IP strategy in the second half of the year. With money in the bank and a reasonably solid market capitalisation, he added that Xilinx might consider buying failing ASSP companies for their IP: "We'd look for stuff to enhance our growth. We'd want the IP as opposed to going into the ASSP market, where we don't have an inherent advantage. I think it's a good time [to buy] and it will be for three years."

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