ARM aims for power-light MCUs

ARM has launched a low-power processor core it hopes licensees will use to compete with the 8 and 16bit microcontrollers designed for low-standby power.

The most popular product in the market today is Texas Instruments’ MSP430, based on a 16bit core, but that is seeing increased competition now from Silicon Labs, with an 8bit offering, and others. ARM’s claim is that its 32bit Cortex-M0 core is no bigger than other designs and can provide higher performance for the same energy.

“It is only 12,000 gates and offers very low dynamic power and leakage together with 32bit performance,” said Dominic Pajak, product manager for the processor division, adding that for arithmetic-intensive functions, the ability to handle 32bit values involves fewer instructions than if they are split into multiple 8 or 16bit operations.

As the company is expecting the M0 to go into wireless sensor nodes and medical devices where standby power consumption needs to be very low, the company has backed up the normal on-chip registers with state-retention shadow registers. These are made using transistors that leak less than their counterparts in the main logic paths – they switch very slowly so cannot be used for regular logic.

“We have worked very closely with our physical IP division on this, using their standard-cell libraries and the power-management kit,” said Pajak. “They provide a couple of features in the kit, such as the state-retention flip-flops.”

The M0 uses the same instruction set as the M1, which comprises mainly Thumb instructions with a few from the Thumb2 set and was developed for use in programmable logic. But the new core has a similar wake-up controller to that used in the current M3 offering. This allows most of the processor to be put to sleep and woken when an interrupt comes in to allow for very low standby power. ARM says the FPGA-based M1 can be used to prototype code for the M0.

ARM expects a number of licensees that decide to use the M0 to opt for one of the ultra-low leakage 0.18µm processes that have appeared in recent years. However, the use of state-retention registers for when the core is sleeping will also suit usage alongside bigger processors, such as the Cortex A8 and A9 in mobile phones and netbooks, which will use 65nm and later processes where leakage is a much greater problem. For use alongside mixed-signal circuits, the M0 is likely to turn up on 0.25µm and 0.35µm processes, where leakage is low enough to make the use of state-retention registers marginal.

On the TSMC 180ULL process, the core consumes around 85µW/MHz, dropping to 12µW/MHz on a 65LP process, according to Pajak. The consumption of the memories and peripherals will need to be added to this to allow a comparison with existing 8 and 16bit microcontrollers.

Pajak said he expects customers making SoCs to use the M0 as a peripheral controller to save power when dealing with a growing number of sensors, such as touchscreen controllers, brightness detectors and accelerometers. “If somebody brushes the touchscreen, for example, the M0 can determine whether it was accidental or deliberate without having to wake up the applications processor,” Pajak explained. “And with sensors such as MEMS accelerometers, there is a requirement to do preprocessing of the data they send out.”

One of the first products to use the M0 is the Mocha to be produced by Triad Semiconductor, which takes a similar approach to the PSoC made by Cypress Semiconductor. The Mocha couples the processor with a programmable analogue array and other peripherals.

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