The crystal method

The hunt for more performance at 22nm is focusing attention on the silicon crystal itself, E&T reports.

Chipmakers are going back to the beginning of the integrated-circuit (IC) industry to find techniques that can boost performance in chips as transistors scale into the nanometer generation. New processing techniques and a better understanding of the quantum-mechanical behaviour of highly scaled devices are helping to re-open avenues that were closed off in the late 1960s, as researchers revealed at the International Electron Devices Meeting last December.

In one direction, some researchers have spent the past five years working out whether silicon wafers should be cut in a different way to boost the performance of the slowest form of transistor made using a CMOS process.

Having used the same crystal surface for some 30 years, fab owners are looking forward to a different orientation to maintain transistor performance as they scale down to the 22nm process node.

The work follows on from models that have provided a much greater understanding of electron and hole mobility based on the direction of the silicon crystal lattice and what happens when it is put under strain.

Although once seen as an exotic technique, rotating the silicon crystal lattice from the conventional (100) direction used for almost all chips to the (110) direction now looks to be "low-hanging fruit" for the industry, according to Vivek Subramanian, technical programme chair for the International Electron Device Meeting (IEDM) and a professor at the University of California at Berkeley.

To a limited extent, chipmakers have already used crystal orientation to alter the performance of transistors. Dick James, Chipworks, says about half the 65nm chips the company has analysed to date have rotated the wafer so that transistors are laid out along a different axis - <110> instead of <001> - to improve transistor performance. This is a relatively simple change as the base wafers are the same but the registration mark cut into it just means that the crystal orientation has been rotated relative to the transistor channel's axis.

The next shift will use a more extensive change in crystal orientation that effectively lowers the density of silicon atoms on the wafer's surface. Researchers use wafers that are cut at an angle to the axis of the source ingot. It is not the first time the silicon crystal angle has changed - in the 1960s, before NMOS transistors prevailed, the favoured crystal surface was (111) and not (100).

The favoured crystal direction for the future is to use the (110) surface. The main advantage of using the (110) silicon surface instead of the conventional (100) orientation is that it boosts the mobility of carriers in PMOS transistors by close to 40 per cent.

Holes, the majority carriers in p-channel transistors, tend to have much lower mobility than electrons, especially in conventional (100) surface silicon, which makes it difficult to achieve the same current drive as for the n-channel devices where conduction-band electrons are the primary charge carriers.

The only way to balance up the current drive - important for switching speed in CMOS - is to make the p-channel wider and therefore larger than n-channel versions. The result is a reduction in circuit density that CMOS designers have had to live with since its introduction in the early 1970s.

The reason for the difference in mobility between lattice oreintations still remains unclear, although researchers are getting close to an answer. The main reason is that the band energy of holes and electrons changes with crystal direction, which leads to a larger or smaller effective mass for each depending on the direction, which can help explain the difference in mobility. However, predicting the changes in hole mobility is not easy and researchers have found complex interactions.

The rotation comes at a cost: worsened NMOS performance. Hidenobu Fukutome of Fujitsu says the degradation can be as much as 30 per cent.

One approach proposed by IBM at previous IEDMs was to combine wafers. They performed a delicate piece of wafer surgery that put (110) silicon wells into a (100) SOI wafer and made n- and p-channel transistors that took advantage of the two different silicon surfaces. However, such wafer-bonding techniques are expensive. So, researchers looked to alternative ways to deal with the NMOS penalty of (110) wafers.

Silicon migration

"We considered if there are any simple candidates to overcome this," says Fukutome. The Fujitsu engineers used a combination of annealing techniques, which Fukutome called silicon migration, and aluminium implantation to restore the performance of the NMOS devices in a test process.

The silicon migration acts to smooth the surface and also curves the top of the channel, effectively making the transistor narrower, which provided a gain in current drive for the NMOS transistors at the cost of higher leakage. To counteract the rise in junction leakage, Fujitsu implanted aluminium in the NMOS transistors.

"We expect that this process could be introduced for high-k, metal-gate in the next generation process," says Fukutome.

Paul Packan of Intel claims for actual processes, the performance degradation will not be as bad as predicted, again because smaller channels don't suffer as badly. However, the change in orientation alters the types of strain that chipmakers need to boost transistor speed.

"For short gate lengths, NMOS drive currents on (110) are not degraded as much as many believe. But we need to know more about the physics to have confidence in these results," says Packan. Smaller devices only saw a degradation of 13 per cent, he remarks, largely because of confinement effects.

Lower degradation

"As you get to narrow devices, you get less degradation," Packan says. "We operate devices around a half micron or less so the degradation is much lower than we expected."

The results for PMOS are impressive, claims Packan, who says the company had demonstrated a drive current of 1.2mA/µm. "That is a record for this type of device."

Ken Shimizu, University of Tokyo, says confinement played a major role in the performance of (110) silicon-on-insulator transistors that use very shallow channel regions.

Although the use of (110) silicon will mean changes in the way that suppliers grow their wafers, the modification is relatively straightforward, says James. All that needs to change is the orientation of the crystal seed around which the silicon ingot forms. At the moment, researchers use wafers cut at an angle from regular ingots.

Today, the results have been achieved on processes that have not been optimised for manufacture and so do not use all the aggressive strain techniques that may be needed for full production. At IEDM several years ago, strained-silicon pioneer MIT's Gene Fitzgerald warned of potential problems with changes to crystal orientation.

Fitzgerald claims the conventional (100) orientation prevents dislocations from growing too far. With strain engineering, crystal dislocations are an occupational hazard and the problem gets worse as engineers investigate more exotic ways of straining silicon for improved mobility. The more exotic materials tend to exhibit large numbers of crystal dislocations, something that Intel and Qinetiq found with trying to grow materials such as indium antimonide on top of GaAs. These materials may wind up being used on top of silicon in future processes thanks to their high mobility.

"If you do this on a (110) or (111) surface, dislocations are a real problem," he claims. "Going off (100) could be a problem."

Subramanian says problems with future materials may not be too much of an issue as long as changes such as crystal orientation keep the industry on track for a generation or two. He points out that chipmakers did not like to work on a technique that could not be used for more than several generations. "Now, they will work on techniques that will only last for one," he claims. The (110) surface may be a single-generation booster while the industry works on alternatives such as putting exotic materials on top of silicon for future generations.

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