Wafer twist beckons for silicon

Chipmakers look increasingly likely to put a twist in the way they use silicon. Having used the same crystal surface for some 30 years, fab owners looking forward to a different orientation to maintain transistor performance as they scale down to the 22nm process node.

Although once seen as an exotic technique, rotating the silicon crystal lattice from the conventional (100) direction used for almost all chips today to the (110) direction now looks to be “low-hanging fruit” for the industry, according to Vivek Subramanian, technical programme chair for the International Electron Device Meeting (IEDM) and a professor at the University of California at Berkeley.

Dick James, senior technology analyst at Chipworks, said about half the 65nm chips the company has analysed to date have rotated the wafer to use a different crystal orientation to improve PMOS transistor performance. But the next shift will use a more extensive change in crystal orientation that effectively lowers the density of silicon atoms on the wafer’s surface.

The main advantage of using this (110) silicon surface is that it boosts the mobility of carriers in PMOS transistors by close to 40 per cent. But it comes at a cost: worsened NMOS performance. Hidenobu Fukutome of Fujitsu said the degradation can be as much as 30 per cent.

“We considered if there are any simple candidates to overcome this,” said Fukutome. The Fujitsu engineers used a combination of annealing techniques, which Fukutome called silicon migration, and aluminium implantation to restore the performance of the NMOS devices in a test process.

The silicon migration acts to smooth the surface and also curves the top of the channel, effectively making the transistor narrower, which provided a gain in current drive for the NMOS transistors at the cost of higher leakage. To counteract the rise in junction leakage, Fujitsu implanted aluminium in the NMOS transistors.

“We expect that this process could be introduced for high-k, metal-gate in the next generation process,” said Fukutome.

Paul Packan of Intel claimed for actual processes, the performance degradation will not be as bad as predicted, again because smaller channels don’t suffer as badly. However, the change in orientation alters the types of strain that chipmakers need to use to boost transistor speed.

“For short gate lengths, NMOS drive currents on (110) are not degraded as much as many believe. But we need to know more about the physics to have confidence in these results,” said Packan. Smaller devices only saw a degradation of 13 per cent, he remarked, largely because of confinement effects.

“As you get to narrow devices, you get less and less degradation,” Packan said. “We operate devices around a half micron or less so the degradation is much lower than we expected.”

The results for PMOS are impressive, Packan claimed, who said the company had demonstrated a drive current of 1.2mA/µm. “That is a record for this type of device,” said Packan.

Ken Shimizu of the University of Tokyo said confinement played a major role in the performance of (110) silicon-on-insulator transistors that use very shallow channel regions.

Although the use of (110) silicon will mean changes in the way that suppliers grow their wafers, the modification is relatively straightforward, said James. All that needs to change is the orientation of the crystal seed around which the silicon ingot forms. At the moment, researchers investigating the performance of (110) silicon use wafers cut at a angle from regular ingots.

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