Intel and TSMC fight for density
IBM and TSMC vied for the prize of densest process at this year’s International Electron Device Meeting (IEDM), with TSMC switching its presentation at the last minute to present results obtained for what the company calls its 28nm process and Intel securing a late paper position in an already crowded session on advanced CMOS technologies.
In its presentation, Intel offered metrics but - perhaps not that surprisingly - little detail on how they had been achieved. Indeed, of four questions tabled later by IEDM delegates, some were not answered at all. None was answered in its entirity.
Sanjay Natarajan, a member of the company’s logic technology development group, said that contacted gate length pitch was 112.5mn: “The tightest recorded for any 32nm process.” This is also ahead of TSMC’s claimed length for its 28nm process of 117nm.
Other key Intel data released included an SRAM cell size of 0.171um2 and an array density of 4.2Mb/mm2. However, TSMC claimed a smaller cell size of just 0.13µm2.
Natarajan said that these three metrics showed a consistent scaling multiple since 90nm: 0.7x for gate length, 0.5x for SRAM cells and 2.2xfor overall area scaling. He suggested that this combination was central to his company’s continued adherence to the Moore’s Law performance calendar.
Intel did not respond directly to TSMC’s surprise 28nm disclosures. Instead, Natarajan used his IEDM presentation to rebut claims that its gate-last strategy since 45nm is more expensive and yields below rival gate-first techniques.
“It adds just 4 per cent to process costs [at 35nm], just as it did at 42nm,” he said. “We believe that is well justified for the performance leadership it enables." Natarajan added that yield at 45nm had been the best for any process.
He said that test runs for 32nm were following the same “two-year cadence on yield learning,” suggesting so far that the company will achieve comparable yield on the new process as it enters volume production in the second half of 2009.
Carlos Diaz, director of advanced technology at TSMC, said the results obtained so far with the 28nm meant “we are pretty much on track to support 28nm volume production”.