CEA-LETI cuts variation with SOI

CEA-LETI has claimed it has broken the record for device-matching characteristics using a silicon-on-insulator process.

The research centre obtained a threshold voltage variation of around 1mV.µm, well below the level obtained in bulk silicon technologies, while maintaining good Ion and Ioff characteristics. The threshold voltage variation of less than 40mV across a wafer was also reported for 25nm gate-length fully depleted SOI (FDSOI) devices using undoped channels and high-k and metal gate stacks.

The work, carried out together with ST Microelectronics and Soitec within the frame of the MEDEA+ DECISIF project, made use of the SOI process flow available in the CEA-LETI facilities in Grenoble. The device results indicated that the undoped channel FDSOI device with high-k/metal gate stack is a valid approach to reducing variability issues at 22nm and below.

Comprehensive results of the influence of Si thickness, strain and process on the variability will be presented at the IEDM 2008 conference in December.

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