Intel goes to immersion with 32nm

Intel will take the wraps off its new 32nm process technology for microprocessors at the International Electron Device Meeting (IEDM) in December.

Intel claimed it is onto a second-generation high-k/metal gate technology and will, for the first time, adopt 193nm immersion lithography to scale down the gate length. The company claimed its process has the highest drive currents reported to date for a 32nm technology. The NMOS saturated drive current is 1.55mA/µm while the corresponding PMOS value is 1.21mA/µm.

Intel researchers used the process to build the largest fully functional SRAM array yet reported: a 291Mb SRAM array test chip with a cell size of 0.171µm2 and an array density of 4.2 Mb/mm2. The test chip operated at 3.8GHz at 1.1 V.

Also at the conference, researchers from HRL Laboratories will describe a possible shortcut to put the high speed of indium phosphide-based transistors into CMOS chips. They built entire wafers of high-performance 250nm double-heterostructure bipolar transistors able to switch at up to 300GHz on IBM’s 130nm RF-CMOS technology.

A partially fabricated wafer is bonded to a full-thickness, but smaller, InP epitaxial wafer. The InP wafer first is temporarily bonded to a handle wafer which allows the InP growth substrate and etch-stop layers to be removed. An aluminum heat-spreader layer is deposited as a blanket film, then the InP DHBT layers are permanently bonded to the IBM CMOS wafer’s top surface. In a first, the CMOS transistors showed no sign of degradation, while the InP transistors showed only minor performance impacts.

A further late paper is work from Tohoku University where magnetic tunnel junctions (MJTs) rather than SRAM cells are used to store data in a high-density 3D processor architecture. The researchers used the MTJs to construct a spin-transfer torque memory. Then, they used the spin-memories to drive reconfigurable 3D logic blocks fabricated with a standard 0.14µm CMOS process.

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