IMEC demonstrates working TSV 3D chips
Research institute IMEC has demonstrated functional 3D integrated circuits obtained using die-to-die stacking using 5µm copper through-silicon vias (TSV).
The institute will now further develop 3D stacked chips on 200mm and 300mm wafers, integrating test circuits from partners participating in its 3D integration research program.
The dice were realised on 200mm wafers in IMEC’s reference 0.13µm CMOS process with an added copper-TSV process. For stacking, the top die was thinned down to 25µm and bonded to the landing die by Cu-Cu thermocompression. IMEC is scaling up the process for die-to-wafer bonding and is on track for migrating the process to its 300mm platform.
To evaluate the impact of the 3D flow on the characteristics of the stacked layers, both the top and landing wafers contained CMOS circuits. Extensive tests confirmed that the performance of the circuits does not degrade with adding TSVs and stacking. And to test the integrity and performance of the 3D stack, ring oscillators with varying configurations were made, distributed over the two chip layers and connected with the TSVs.
“With these tests, we have demonstrated that our technology allows designing and fabricating fully functional 3D SIC chips. We are now ready to accept reference test circuits from our industry partners,” said Eric Beyne, IMEC scientific director for 3D technologies, “This will enable the industry to gain early insight and experience with 3D SIC design, using their own designs.”