IBM and Mentor to compute their way to 22nm

IBM and Mentor Graphics have decided to pool resources on a project to push 193nm lithography to produce chip designs for the forthcoming 22nm process, which is expected to start ramping for production in a couple of years.

The deal will see the two companies work on software that will perform advanced forms of optical correction of the features on chipmaking masks, under the banner of ‘computational lithography’. Although Mentor has worked with IBM on optical proximity correction (OPC) since the introduction of the 130nm process, it is the first time that the companies have decided to jointly develop this type of software.

“Ever since the 130nm process, 193nm lithography has been used and there has been a litany of efforts to replace it, but none have succeeded yet. But some of the knobs [to extend the life of 193nm lithography] that were provided by the equipment providers are no longer available at 22nm. With immersion lithography, the numerical aperture seems to be maxed out at 0.35. And the worldwide effort to increase the refractive index of lenses and fluids seems to have reached its limit,” said John Sturtevant, director of technical support for Mentor’s design-to-silicon business unit.

Although double patterning provides a way to extend the lifetime of 193nm lithography, IBM and Mentor believe there is scope to use another technique to define smaller features that uses alterations to the layout and the way that the mask is lit inside the lithographic stepper.

“We have to go beyond projection optics and more into illumination optics. Almost all of the attention has been on projection optics, but you get additional degrees of freedom from the illumination optics,” Sturtevant claimed.

Today’s steppers have the ability to change the shape of the light source, which alters the way that the features of the mask cast a shadow on the chip’s surface. Typically, said Sturtevant, the lighting will be defined early on in the lifetime of a process for each mask layer and never changed. IBM and Mentor aim to produce software that will calculate the best light source form for a given design and, on top of that, make modifications to the layout to improve how the image prints. The companies have called the technique source-mask optimisation (SMO).

“In the past, memory arrays have been the obvious targets for this technology. But together, we will be leveraging some breakthough mathematical approaches that will allow global optimisations to be performed even for random logic,” said Sturtevant. “Even though there is a huge range of shapes [in random logic layouts], we believe that the optimisation will improve the worst case scenario for that design.”

To perform the calculations, Mentor will use hardware acceleration. The company already uses the IBM Cell in processor arrays for its current generation of OPC tools. “The starting point is the Cell but we are looking at all the different hardware optimisation platforms. And we want to make sure it is on the most cost-effective platform. The technique has a huge computational burden: it would not have been possible to use previously.”

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