Accellera updates mixed-signal Verilog

Design automation standards-development group Accellera has approved a new version of its Verilog-Analogue Mixed-Signal (AMS) standard: Verilog-AMS 2.3.

The new version of the standard unifies the Verilog-AMS 2.2 specification with the 2005 version of the IEEE1364 Verilog hardware description language (HDL) standard for digital design. The previous Accellera Verilog-AMS standard, Verilog-AMS 2.2, was approved in 2005.
“The Verilog-AMS 2.3 language release is an important milestone for our Technical Committee and the industry at large,” said Shrenik Mehta, Accellera chairman. “A unified Verilog-AMS language integrated with the IEEE Verilog standard improves AMS design and will result in an increased acceptance of the standard.”
Apart from IEEE1364 integration, Verilog-AMS 2.3 introduces new analogue and mixed-signal features to support and enable improved top-down AMS design and verification methodologies. These include support for multiple analogue blocks and the resolution of language conflicts with the SystemVerilog as defined in IEEE P1800. The alterations include changing the digital domain name to 'ddiscrete' from 'logic' as logic is a keyword in SystemVerilog.
The next phase of Accellera’s AMS technical activities will include integration of the AMS standard with the SystemVerilog language, and extensions to the AMS language for mixed-signal assertions and behavioural modeling support.

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