Military project aims to put graphene into radios
HRL Laboratories, a research joint venture owned by Boeing and General Motors, has said it will work on making transistors from graphene as part of a military project to create high-frequency radios.
HRL is joining the Carbon Electronics for RF Applications (CERA) programme sponsored by the US Defense Advanced Research Projects Agency (DARPA). Under the management of the Navy's Space and Naval Warfare Systems Center (SPAWAR) in San Diego, California, HRL will work with a group of university, commercial and military research centres on the proposed 51-month program, which will consist of three phases to develop graphene-based RF circuits for ultra-high-speed, ultra-low-power applications.
“Graphene is a highly interesting material, and a technology based on a graphene-on-silicon platform could revolutionise a number of military applications because of its high performance, scalability, integration, and low cost,” claimed Jeong-sun Moon, senior research scientist with the microelectronics laboratory at HRL. “This new generation of transistors will provide the military community with better than state-of-the-art radio frequency components that have unprecedented capabilities.”
The development of sophisticated military imaging systems and high-bandwidth communications systems has been hampered by RF component cost, limited resolution, and high power dissipation. By exploiting the unique qualities of graphene, the HRL team reckons it can change the way these systems are developed and powered at the integrated-circuit level.
Graphene is a single layer of carbon atoms densely packed in a honeycomb structure. The team aims to grow a layer of graphene carbon crystals on silicon-based wafers to create transistors.
During the first phase of the project, HRL will perform graphene synthesis using a carbon molecular-beam epitaxy process developed by HRL to deposit a single crystalline layer of graphene carbon onto a silicon substrate. The following two phases of the project will fabricate field-effect transistors on 100mm wafers and then scale up the process for 200mm wafers.