TSMC opsns up on yield projections

Taiwanese foundry TSMC has decided to start providing chip creators with much more information about its processes, using custom software that the foundry will plug into design tools. By putting the software into the design tools, the company believes it can provide much better pointers to how chips will yield on the production line without disclosing information on its processes to competitors.

Historically, foundries have been reluctant to provide detailed information on the conditions that affect chip yield as that can provide clues not just on process conditions but profitability. But this approach runs counter to the needs of the new wave of design-for-manufacturing (DFM) tools.

One of the problems with DFM tools is that they require detailed information about the sources of defects from fabs and foundries to be able to provide accurate predictions. TSMC originally dealt with the problem by providing the EDA vendors with encrypted databases that the tools could read to determine whether a circuit layout might unnecessarily lead to manufacturing defects.

In recent years, the database approach has started to break down, claimed Tom Quan, deputy director of design service marketing at TSMC: “Going down to 32nm, manufacturing variances are increasing. Prediction and manufacturing are diverging. We have been seeing it a little bit at 45nm but, at 32nm, it becomes a big issue.”

The problem, claimed Quan, is that the fixed data can only go so far: simulation of the effects of layout are becoming more important. So, the company has decided to provide some of the software it has developed internally to model hotspots, and which are used today to build the encrypted databases. “In this architecture, we encapsulate not just the data but the actual DFM engine. Customers still download it from us but we work with the vendors to allow their tools to work with it. We let the vendors use an API to talk to the engine. That is really the core innovation: we no longer just deliver the data but the whole engine. We are talking a bolder step now by providing a full production recipe.”

The software performs checks to ensure that all accesses are through the APIs and keys provided to the EDA vendors to prevent the engine from being ‘mined’ for details on the processes. By providing the DFM engine, TSMC aims to provide forward-looking information about yield. Among the three modules, there is an engine that performs critical area analysis (CAA) a technique for estimating the effects of random defects on yield.

“Before, CAA contained mainly historical data on random defects. Now we have the forecast data. We are providing the data to forecast [random defect probabilities] for up to eight quarters, plus all the systematic defects,” said Quan.

The idea behind the forecast data is to allow high-volume chipmakers to estimate how much they need to take account of random defects over the lifetime of an integrated circuit. Rather than use a less dense design that tolerates higher defect densities at an early part of the process ramp, they can aim for a lower defect density predicted by TSMC’s estimates of its ability to reduce them over time, and take the cost advantage of a smaller die. The customer might lose a higher percentage of parts during sampling but as it goes into production, the die should be more cost-effective than a more conservative design.

The other software modules analyse the effects of chemical mechanical polishing (CMP) and lithography. The CMP module concentrates primarily on the upper metal layers. “Metal three and down are inside the cells,” said Quan, so their behaviour under CMP will be simulated more extensively during library design rather than at the end of the chip-design phase.

“Up until last year, people had a lot of metal-fill algorithms but they weren’t very smart. If you overfill, you increase the capacitance. With the CMP engine we can more smartly deliver patterns of where things should be done. This will help deliver a better picture. Increasingly, we are moving from taking care of physical DFM to more electrical DFM: how it affects power and timing, for example,” Quan explained.

Recent articles

Info Message

Our sites use cookies to support some functionality, and to collect anonymous user data.

Learn more about IET cookies and how to control them