Intel looks to one-transistor memory beyond 20nm
Intel has developed a single-transistor memory that its developers reckon will be denser and could be easier to make than conventional SRAM on the processes that the company will be using in the next decade.
Following work on a vertical memory transistor unveiled at the International Electron Device Meeting (IEDM) 18 months ago, Intel said at the VLSI Technology Symposium in Hawaii this week (17 June) it had successfully made planar, single-transistor memory cells of a size that would fit the demands of a 16nm process.
“We have been able to make devices with a gate length down to 30nm. That would translate to a cell size that is 0.01µm2 or less. That is more than a factor of 30 smaller than the cache memory on the 45nm node that we are shipping today,” claimed Mike Mayberry, director of components research and vice president of the technology and manufacturing group at Intel. “We can publish good retention results and this work is two generations smaller than anything anyone has published so far.”
Other companies such as Innovative Silicon, which has licensed its technology to AMD and Hynix, and Toshiba have made single-transistor memory test chips using a planar structure. Intel initially used a vertical approach because it considered that approach to be more manufacturable. However, the researchers decided they would need to investigate a planar structure.
“If we did a vertical transistor for the logic, then it would be difficult to do a planar transistor for the memory, and vice versa. The implementation of the two are somewhat coupled,” Mayberry explained. “And we want to explore an area that is difficult to explore with the vertical structure. With the vertical transistor, the two sides of the structure have to be the same. With a planar device, we can make the top layer different to the bottom layer.”
All of today’s floating-body cell memories, such as those made so far by Intel, ISI and Toshiba call for the use of silicon-on-insulator (SOI) wafers. Although AMD has opted to use SOI, Intel and others have said that the wafers are too expensive to be viable. ISI is working on varieties of floating-body cells based on vertical transistors such as finFETs that do not need to be placed on SOI wafers. However, for a planar structure, SOI is almost essential. But the use of the cell may not force Intel to use SOI wafers: the company will look at ways to introduce the necessary buried oxide locally.
“Once we figure out the optimum structure, we can figure out other ways of integrating, including [the use of] a local buried oxide,” said Mayberry.
Mayberry said there are significant manufacturing issues with the planar structure although the devices, including a memory cell that would fit the requirements of the 10nm node, could all be made using the same lithographic techniques as today’s 45nm process. “The kind of SOI we use is very thin it allows us to use a lower voltage. Not only does that mean problems with creating the film in the first place, but there are also issues with making contact to those thin layers; being able to land on the 22nm-thick silicon layer without punching through.”
So far, Intel has only made isolated cells. “The next step would be to make a large array to sample the process variability,” said Mayberry.
Image: Cross-section of Intel's floating-body cell. The pale SOI layer is 10nm thick, lying underneath a 22nm thick layer of silicon