Chip stacks get water cooling
Researchers from IBM and the Fraunhofer Institute in Berlin have demonstrated a prototype cooling system for 3D chips that pipes water between each layer in the stack.
The problem with chip stacks and the reason why many of them are memory-only is that heat dissipation becomes a major problem when two chips with high power demands are stacked on top of each other: the heat from one has to pass through the other to make it to the heatsink or a heat-spreading plane in the PCB.
“As we package chips on top of each other to significantly speed a processor’s capability to process data, we have found that conventional coolers attached to the back of a chip don’t scale. In order to exploit the potential of high-performance 3D chip stacking, we need interlayer cooling,” said Thomas Brunschwiler, project leader at IBM’s Zurich Research Laboratory. “Until now, nobody has demonstrated viable solutions to this problem.”
Brunschwiler and his team piped water between the individual chip layers, relying on silicon-dioxide walls around the interchip connections to prevent water interfering with the electrical signals. The team was able to demonstrate a cooling performance of up to 180W/cm2 per layer for a stack with a typical footprint of 4cm2.
“With classic backside cooling, the stacking of two or more high-power density logic layers would be impossible,” said Bruno Michel, manager of the chip cooling research efforts at the IBM Zurich Lab.
In the experiments, the scientists piped water through a 1 by 1cm test setup, consisting of a cooling layer between two dies or heat sources. The cooling layer is about 100µm in height and is packed with 10,000 vertical interconnects per square centimetre. They use through silicon vias to form the interchip connections.
Brunschwiler, with colleagues from the Fraunhofer Institute, developed a thin-film soldering technique to join the two chips and seal the connections. In the test setup, the assembled stack was placed in a silicon cooling container resembling a miniature basin. The water was pumped into the container from one side, flowing between the individual chip layers before exiting at the other side.
Using simulations, scientists extrapolated the experimental results of their test vehicle to a 4cm2 chip stack and achieved a cooling performance of 180W/cm2.
In further research, Brunschwiler and his team are working to improve the cooling system for smaller chip dimensions and more interconnects. They are also investigating sophisticated structures for hotspot cooling.
Image: IBM wants to cut the cost of cooling the high-density chips in data centres by going back to water cooling