Synopsys hands VMM material to Accellera

Synopsys has decided to donate to standards group Accellera the library and the software that the company uses to back up its VMM verification methodology, which is used to check chip designs using the SystemVerilog language.

Accellera has accepted the donation so the recently formed Accellera Verification IP (VIP) technical subcommittee. Synopsys claimed VMM has been used successfully by hundreds of verification teams since its introduction in 2005. The VMM competes with the OVM methodology created as a result of the decision by Cadence Design Systems and Mentor Graphics to merge their own respective verification methodologies.

“Accellera’s newest standardisation activity will promote interoperability among vendors’ and users’ verification methodologies,” said Shrenik Mehta, Accellera chair. “The donation of Synopsys’ VMM implementation provides the technical subcommittee with established technology to meet their objectives.”

Manoj Gandhi, senior vice president and general manager of the verification group at Synopsys, claimed: “Accellera’s acceptance of Synopsys’ donation of its complete implementation of the VMM methodology enables Accellera to leverage this investment to create a single, unified standard that will accelerate the pace of innovation.”

Synopsys said it has donated its complete implementation of the VMM methodology, which includes a standard library of verification components and all the applications that Synopsys has sold to customers using VMM.

Image: Accellera hopes to streamline IC design by allowing verification techniques to interoperate

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