Synopsys builds interface for TSMC process models
Synopsys has released its TSMC Modeling Interface (TMI) methodology, which has been developed from the company’s protocol for integrating custom device models into its HSpice, HSim and NanoSim transistor-level circuit simulators.
Synopsys claimed the TMI methodology delivers an efficient device modeling approach for TSMC’s process technologies at 40nm. This methodology, on average, improves simulation time and reduces memory usage by five times.
“To accurately model MOSFET transistors at 40nm and below, TSMC is exploring new modeling methodologies that deliver the best simulation performance without accuracy changes,” said Min-Chie Jeng, director of the advanced technology modeling division at TSMC. “With the development of the TMI specification and computer software, TSMC overcomes the limitations of the sub-circuit macro modeling approach that has been in use for several generations of technology nodes. This leads to improvements in both 40nm computer simulation time and memory usage.”
With device geometries shrinking at every new process node, MOSFET model complexity has increased in order to accurately represent the impact of new physical effects. At 40nm, the industry-standard BSIM4 MOSFET model must now take into consideration mechanical stress effects in silicon, and layout dependencies that alter the characteristics of individual device instances based on their placement and proximity to other devices. Standardisation of stress-effect modeling is extremely difficult because of the differences that exist in each application of strain engineering, and requires customisation of models for every process.
Some companies have found that silicon and simulation are diverging at these nodes. Paul Hollingworth, senior director of Altera’s HardCopy product group, said the company’s transceiver test chips for its upcoming Stratix 4 field programmable gate arrays showed asymmetric waveforms because of the effect of strain on p-channel transistors in the 40nm process. Dense layouts tend to reduce the amount of strain in p-channel transistors, which slows them down compared with those that are surrounded by large areas of diffusion.
Paul Lo, senior vice president and general manager of the analogue and mixed signal group at Synopsys, claimed: “The success of this joint effort with TSMC has again demonstrated Synopsys’ commitment to provide the most advanced device modeling and circuit simulation performance for the latest generation of silicon technology. In addition, the TMI methodology, based on Synopsys’ protocols, establishes the foundation for TSMC’s Spice Tool Qualification Programme, which we anticipate will become an industry standard.”
Image: The Spice modelling interface is meant to improve accuracy on advanced nodes